Increasing the number of I/O decode ranges using SMI traps
First Claim
1. A method of increasing the quantity of input/output (I/O) decode ranges in a chipset, comprising:
- generating a system management interrupt (SMI) based on information causing access to an I/O address that triggers a SMI trap, the I/O address operably received at the chipset via a bus; and
automatically reprogramming a decode register in the chipset such that the I/O address forwards the information to a device on the bus.
14 Assignments
0 Petitions
Accused Products
Abstract
A method of increasing the quantity of input/output (I/O) decode ranges using system management interrupts (SMI) traps is disclosed. In one aspect, the present disclosure teaches a method of increasing the quantity of I/O decode ranges using SMI traps in a chipset including generating a system management interrupt (SMI) based on information causing access to an I/O address that triggers a SMI trap. The I/O address operably received at the chipset via a bus. The method further including automatically reprogramming a decode register in the chipset such that the I/O address forwards the information to a device on the bus.
24 Citations
20 Claims
-
1. A method of increasing the quantity of input/output (I/O) decode ranges in a chipset, comprising:
-
generating a system management interrupt (SMI) based on information causing access to an I/O address that triggers a SMI trap, the I/O address operably received at the chipset via a bus; and
automatically reprogramming a decode register in the chipset such that the I/O address forwards the information to a device on the bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. An information handling system, comprising:
-
a processor;
a memory coupled to the processor;
a chipset communicatively coupled to the processor and the memory such that the chipset operably receives input/output (I/O) address from the processor via a bus;
the chipset including a decode register having at least one decode range, the decode range operable to route information to a computer device associated with the decode range;
a stored decode register communicatively coupled to the chipset, the stored decode register operably stores an I/O address; and
a system management interrupt (SMI) trap operably set to generate a SMI, whereby during the SMI, a SMI handler reprograms the decode register to include at least one of the I/O addresses to allow the information to be forwarded to the respective computer device on the bus. - View Dependent Claims (12, 13, 14, 15)
-
-
16. A computer-readable medium having computer-executable instructions for performing a method of increasing the quantity of input/output (I/O) decode ranges, comprising:
-
programming a system management interrupt (SMI) trap in a basic I/O system (BIOS) to generate a SMI, the SMI trap operably triggered from information accessing an I/O address;
upon generation of the SMI, saving a current value of a decode range register in memory and deactivating the SMI trap;
automatically reprogramming a decode range register to include the I/O address;
following the reprogramming of the decode range register, resending the information accessing the I/O address and restoring the decode range register to the current value; and
re-activating the SMI trap. - View Dependent Claims (17, 18, 19, 20)
-
Specification