Virtual-to-physical address translation in a flash file system

• US 20060026341A1
• Filed: 01/03/2005
• Published: 02/02/2006
• Est. Priority Date: 07/30/2004
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: M-Systems Flash Disk Pioneers Ltd. (Western Digital Corporation)
• Inventors: Lasser, Menahem
• Granted Patent: US 7,386,700 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10

Abstract

A flash memory management system for a memory for accessing data from a host, the system including physical units and virtual units of the memory and a mapping mechanism of each virtual unit into one or more physical units, wherein the number of binary bits required for accessing each of the virtual units is less than the number of binary bits required for accessing each of the physical units.

Claims

1. A flash memory management method for a flash memory for accessing data from a host, the method comprising the steps of:

(a) providing a physical address space of the flash memory, said physical address space addressable with a plurality of physical addresses;

(b) providing a virtual address space of the flash memory, said virtual address space addressable with a plurality of virtual addresses; and

(c) mapping said virtual addresses into said physical addresses, wherein the number of binary bits required for accessing each of said virtual addresses is less than the number of binary bits required for accessing each of said physical addresses.

2. A flash memory management method for a flash memory for accessing data from a host, the method comprising the steps of:

(a) providing a plurality of physical units of the flash memory;

(b) providing a plurality of virtual units of the flash memory;

(c) mapping each of said virtual units into at least one of said physical units,

wherein the number of binary bits required for addressing each of said virtual units is less than the number of binary bits required for addressing each of said physical units.

3. A flash memory management system for a flash memory for accessing data from a host, the system comprising:

(a) the flash memory addressable with a plurality of physical addresses;

(b) a plurality of virtual addresses; and

(c) a mapping mechanism of said virtual addresses into said physical addresses, wherein the number of binary bits required for accessing each of said virtual addresses is less than the number of binary bits required for accessing each of said physical addresses.

4. A flash memory management system for a flash memory for accessing data from a host, the system comprising:

(a) a plurality of physical units of the flash memory;

(b) a plurality of virtual units;

(c) a mapping mechanism of said virtual units into said physical units,

wherein the number of binary bits required for addressing each of said virtual units is less than the number of binary bits required for addressing each of said physical units.

5. A method of managing a flash memory comprising the steps of, in accessing the flash memory from a host:

(a) addressing the flash memory via a physical address space; and

(b) accepting from said host only addresses from a virtual address space that is smaller than said physical address space,

wherein addresses of said virtual address space have fewer bits than physical addresses of said physical address space.

6. A memory device comprising:

(a) a flash memory; and

(b) a controller that, in accessing said flash memory, addresses said flash memory using a physical address space, and that accepts from a host that addresses the memory device only addresses from a virtual address space,

wherein addresses of said virtual address space have fewer binary bits than addresses of said physical address space.

7. A flash memory device comprising:

(a) a flash memory containing a plurality of physical flash memory units; and

(b) a controller that, in accessing said flash memory, addresses said flash memory using addresses from a physical address space that employs physical units, and that accepts from a host that addresses the memory device only addresses from a virtual address space that employs virtual units,

wherein addressing said virtual memory units requires fewer binary bits than required for addressing said physical memory units.