Memory usable in cache mode or scratch pad mode to reduce the frequency of memory accesses
First Claim
1. A processor adapted to couple to external memory, comprising:
- a controller;
data storage operated by said controller, said data storage configurable to operate in either a cache policy mode in which a miss results in an access of the external memory or in a scratch pad policy mode in which a miss does not result in an access of the external memory;
wherein said data storage comprises a first portion and a second portion, and wherein only one of said portions is active at a time, the non-active portion being unusable; and
wherein, when the active portion does not have sufficient capacity for additional data to be stored therein, the other portion becomes the active portion.
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Accused Products
Abstract
A processor adapted to couple to external memory. The processor comprises a controller and data storage (e.g., cache memory). The data storage is configurable to operate in either a cache policy mode in which a miss results in an access of the external memory or in a scratch pad policy mode in which a miss does not result in an access of the external memory. The data storage comprises a first portion and a second portion, and only one of the portions is active at a time. The non-active portion is unusable to store or retrieve data (e.g., Java local variables). When the active portion does not have sufficient capacity for additional data to be stored therein, the other portion becomes the active portion.
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Citations
22 Claims
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1. A processor adapted to couple to external memory, comprising:
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a controller;
data storage operated by said controller, said data storage configurable to operate in either a cache policy mode in which a miss results in an access of the external memory or in a scratch pad policy mode in which a miss does not result in an access of the external memory;
wherein said data storage comprises a first portion and a second portion, and wherein only one of said portions is active at a time, the non-active portion being unusable; and
wherein, when the active portion does not have sufficient capacity for additional data to be stored therein, the other portion becomes the active portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A system, comprising:
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a communications transceiver;
a first memory;
a controller communicatively coupled to said communications transceiver and said memory; and
a second memory operated by said controller, said second memory configurable to operate in either a cache policy mode in which a miss results in an access of the first memory or in a scratch pad policy mode in which a miss does not result in an access of the first memory;
wherein said second memory comprises a first portion and a second portion, and wherein only one of said portions is active at a time, the non-active portion being unusable; and
wherein, when the active portion does not have sufficient capacity for additional data to be stored therein, the other portion becomes the active portion. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A method, comprising:
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using only a first portion of a cache memory data array to store local variables until said first portion has insufficient capacity for storing additional local variables, said cache memory data array comprising the first portion and a second portion;
once the first portion has insufficient capacity for storing additional local variables, using only the second portion of the cache memory data to store said additional local variables and not using the first portion; and
when the second portion has insufficient capacity for storing additional local variables, copying the local variables from only the first portion to external memory. - View Dependent Claims (21, 22)
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Specification