Power management coordination in multi-core processors

• US 20060026447A1
• Filed: 07/27/2004
• Published: 02/02/2006
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Rotem, Efraim, Naveh, Alon, Weissmann, Eliezer
• Granted Patent: US 7,966,511 B2
• Time in Patent Office: Days
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods of managing power provide for issuing a first operating requirement from a first processor core and issuing a second operating requirement from a second processor core. In one embodiment, the operating requirements can reflect either a power policy or a performance policy, depending upon the factor that is currently most important to software. Hardware coordination logic is used to coordinate a shared resource setting with the operating requirements. The hardware coordination logic is also able to coordinate the shared resource setting with independent resource settings of the first and second processor cores based on the operating requirements.

Claims

1. A processor comprising:

a plurality of cores to issue a corresponding plurality of operating requirements; and

coordination logic coupled to the plurality of cores, the coordination logic to coordinate a shared resource setting of the plurality of cores with the plurality of operating requirements.

2. The processor of claim 1, wherein the coordination logic is to coordinate the shared resource setting with an independent resource setting of at least one of the plurality of cores.

3. The processor of claim 2, wherein the coordination logic is to select the shared resource setting according to a first operating requirement of a first core and a second operating requirement of a second core, the first core to select an adjusted value for the independent resource setting that enables the first operating requirement to be satisfied.

4. The processor of claim 3, wherein the coordination logic is to translate the first operating requirement into a first target value, translate the second operating requirement into a second target value, compare the first operating requirement to the second operating requirement, select the second target value as the shared resource setting if the second operating requirement is greater than the first operating requirement and report a corrected operating requirement that results from the shared resource setting to the first core, the first core to select the adjusted value based on the corrected operating requirement.

5. The processor of claim 4, further including a performance state transition table, the coordination logic to use the performance state transition table to translate the first operating requirement into the first target value and translate the second operating requirement into the second target value.

6. The processor of claim 3, wherein the second core is to issue a modified operating requirement that corresponds to a reduced second target value, the coordination logic to adjust the shared resource setting based on the modified operating requirement, the first core to adjust the independent resource setting based on the adjusted shared resource setting.

7. The processor of claim 2, wherein the independent resource setting is to include a setting selected from a set including an independent clock throttle setting and an architecture throttle setting.

8. The processor of claim 2, wherein the coordination logic is to coordinate a plurality of shared resource settings with a plurality of independent resource settings.

9. The processor of claim 1, wherein the shared resource setting is to include a setting selected from a set including a voltage setting and a frequency setting.

10. The processor of claim 1, wherein the plurality of operating requirements is to include a plurality of power requirements.

11. The processor of claim 1, wherein the plurality of operating requirements is to include a plurality of performance requirements.

12. A method comprising:

issuing a plurality of operating requirements from a corresponding plurality of processor cores; and

coordinating a shared resource setting of the plurality of processor cores with the plurality of operating requirements.

13. The method of claim 12, further including coordinating the shared resource setting with an independent resource setting of at least one of the plurality of processor cores.

14. The method of claim 13, wherein coordinating the shared resource setting with the independent resource setting includes:

selecting the shared resource setting according to a first operating requirement of a first processor core and a second operating requirement of a second processor core; and

selecting an adjusted value for the independent resource setting that enables the first operating requirement to be satisfied.

15. The method of claim 14, wherein selecting the shared resource setting includes:

translating the first operating requirement into a first target value;

translating the second operating requirement into a second target value;

comparing the first operating requirement to the second operating requirement;

selecting the second target value as the shared resource setting if the second operating requirement is greater than the first operating requirement;

reporting a corrected operating requirement that results from the shared resource setting to the first core; and

selecting the adjusted value based on the corrected operating requirement.

16. The method of claim 15, wherein translating the first and second operating requirements includes using a performance state transition table.

17. The method of claim 14, further including:

issuing a modified operating requirement from the second processor core;

adjusting the shared resource setting based on the modified operating requirement; and

adjusting the independent resource setting based on the adjusted shared resource setting.

18. The method of claim 13, wherein the coordinating the shared resource setting with the independent resource setting includes coordinating the shared resource setting with a setting selected from a set including an independent clock throttle setting and an architecture throttle setting.

19. The method of claim 13, further including coordinating a plurality of shared resource settings with a plurality of independent resource settings.

20. The method of claim 12, wherein the coordinating includes coordinating at a setting selected from a set including a voltage setting and a frequency setting.

21. The method of claim 12, wherein the coordinating includes coordinating the shared resource setting with a plurality of power requirements.

22. The method of claim 12, wherein the coordinating includes coordinating the shared resource setting with a plurality of performance requirements.

23. A system comprising:

a clock source having a shared frequency setting; and

a processor coupled to the clock source, the processor having a plurality of cores to issue a corresponding plurality of operating requirements and coordination logic coupled to the plurality of cores, the coordination logic to coordinate a shared frequency setting of the plurality of cores with the plurality of operating requirements.

24. The system of claim 23, wherein the coordination logic is to coordinate the shared resource setting with an independent resource setting of at least one of the plurality of cores.

25. The system of claim 24, wherein the coordination logic is to select the shared frequency setting according to a first operating requirement of a first core and a second operating requirement of a second core, the first core to select an adjusted value for the independent resource setting that enables the first operating requirement to be satisfied.

26. The system of claim 25, wherein the coordination logic is to translate the first operating requirement into a first frequency, translate the second operating requirement into a second frequency, compare the first operating requirement to the second operating requirement, select the second frequency as the shared frequency setting if the second operating requirement is greater than the first operating requirement and report a corrected operating requirement that results from the shared resource setting to the first core, the first core to select the adjusted value based on the corrected operating requirement.

27. The system of claim 25, wherein the second core is to issue a modified operating requirement that corresponds to a reduced second frequency, the coordination logic to adjust the shared frequency setting based on the modified operating requirement, the first core to adjust the independent resource setting based on the adjusted shared frequency setting.

28. The system of claim 24, wherein the independent resource setting is to include a setting selected from a set including an independent clock throttle setting and an architecture throttle setting.

29. The system of claim 23, wherein the plurality of operating requirements is to include a plurality of power requirements.

30. The system of claim 23, wherein the plurality of operating requirements is to include a plurality of performance requirements.

31. A method comprising:

issuing a first operating requirement from a first processor core;

issuing a second operating requirement from a second processor core;

translating the first operating requirement into a first target value;

translating the second operating requirement into a second target value;

comparing the first operating requirement to the second operating requirement;

selecting the second target value as a shared resource setting if the second operating requirement is greater than the first operating requirement;

selecting an adjusted value for an independent resource setting that enables the first operating requirement to be satisfied;

issuing a modified operating requirement from the second processor core;

adjusting the shared resource setting based on the modified operating requirement; and

adjusting the independent resource setting based on the adjusted shared resource setting.

32. The method of claim 31, wherein the shared resource setting includes a setting selected from a set including a voltage setting and a frequency setting.

33. The method of claim 31, wherein the independent resource setting includes a setting selected from a set including an independent clock throttle setting and an architecture throttle setting.