VARIABLE SIGMA ADJUST METHODOLOGY FOR STATIC TIMING

• US 20060026544A1
• Filed: 07/30/2004
• Published: 02/02/2006
• Est. Priority Date: 07/30/2004
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Hayes, Jerry D., Engel, James J.
• Granted Patent: US 7,174,523 B2
• Time in Patent Office: Days
• US Class Current: 716/52
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/3315 using static timing analysis [STA]

Abstract

The invention presents a method of accommodating for across chip line variation (ACLV) and/or changing static timing of an integrated circuit design. The invention first establishes a circuit design having initial timing requirements and an initial voltage supply and also establishes a relationship between gate timing variations caused by voltage supply changes and gate timing variations caused by manufacturing processing changes. Then, according to the customer'"'"'s orders that change the initial timing requirements to revised timing requirements, the invention changes the initial voltage supply to a revised voltage supply to accommodate the revised timing requirements (and ACLV if desired) based on the relationship between voltage limits and transistor delay. This process of changing the initial voltage supply does not alter the circuit design.

Claims

1. A method of adjusting process corners for adjusting timing of an integrated circuit design, said method comprising:

establishing initial voltage sensitivity curves relating to the relationship between gate timing variations caused by voltage supply changes and gate timing variations caused by manufacturing processing changes in a circuit design for slow and fast process extremes;

establishing an initial voltage supply at which initial process corners appear on said voltage sensitivity curves;

establishing revised process corners for which initial timing requirements are to be changed into revised timing requirements;

establishing revised voltage sensitivity curves relating to said revised process corners; and

changing said initial voltage supply to a revised voltage supply to accommodate said revised timing requirements based on where said revised process corners cross said revised voltage sensitivity curves.

2. The method in claim 1, wherein said process of changing said initial voltage supply does not perform any of said manufacturing processing changes.

3. The method in claim 1, wherein transistors in said circuit design are based on a common transistor design.

4. The method in claim 1, wherein said revised timing requirements are used to determine whether manufactured chips are defective.

5. The method in claim 1, wherein said initial timing requirements and said revised timing requirements comprise one of two extreme process corners for said circuit design consisting of either the fastest process timing allowed by said circuit design or the slowest process timing allowed by said circuit design.

6. The method in claim 1, wherein said process of changing said initial voltage supply includes changing said initial voltage supply sufficiently to compensate for across chip line variation (ACLV).

7. The method in claim 1, wherein said revised timing requirements comprise front end process timing requirements associated with said gate delay.

8. A method of adjusting timing requirements of an integrated circuit design, said method comprising:

establishing a circuit design having initial timing requirements and an initial voltage supply;

establishing a relationship between gate timing variations caused by voltage supply changes and gate timing variations caused by manufacturing processing changes;

changing said initial timing requirements to revised timing requirements; and

changing said initial voltage supply to a revised voltage supply to accommodate said revised timing requirements based on said relationship between gate timing variations caused by voltage supply changes and gate timing variations caused by manufacturing processing changes.

9. The method in claim 8, wherein said process of changing said initial voltage supply does not perform any of said manufacturing processing changes.

10. The method in claim 8, wherein said transistors in said circuit design are based on a common transistor design.

11. The method in claim 8, wherein said revised timing requirements are used to determine whether manufactured chips are defective.

12. The method in claim 8, wherein said initial timing requirements and said revised timing requirements comprise one of two extreme process corners for said circuit design consisting of either the fastest process timing allowed by said circuit design or the slowest process timing allowed by said circuit design.

13. The method in claim 8, wherein said process of changing said initial voltage supply includes changing said initial voltage supply sufficiently to compensate for across chip line variation (ACLV).

14. The method in claim 8, wherein said revised timing requirements comprise front end process timing requirements associated with said gate delay.

15. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform a method of changing timing requirements of an integrated circuit design, said method comprising:

establishing a circuit design having initial timing requirements and an initial voltage supply;

establishing a relationship between gate timing variations caused by voltage supply changes and gate timing variations caused by manufacturing processing changes;

changing said initial timing requirements to revised timing requirements; and

changing said initial voltage supply to a revised voltage supply to accommodate said revised timing requirements based on said relationship between gate timing variations caused by voltage supply changes and gate timing variations caused by manufacturing processing changes.

16. The program storage device in claim 15, wherein said process of changing said initial voltage supply does not perform any of said manufacturing processing changes.

17. The program storage device in claim 15, wherein said transistor in said circuit design are based on a common transistor design.

18. The program storage device in claim 15, wherein said revised timing requirements are used to determine whether manufactured chips are defective.

19. The program storage device in claim 15, wherein said initial timing requirements and said revised timing requirements comprise one of two extreme process corners for said circuit design consisting of either the fastest process timing allowed by said circuit design or the slowest process timing allowed by said circuit design.

20. The program storage device in claim 15, wherein said process of changing said initial voltage supply includes changing said initial voltage supply sufficiently to compensate for across chip line variation (ACLV).