Highly integrated single chip set-top box

• US 20060026657A1
• Filed: 07/22/2005
• Published: 02/02/2006
• Est. Priority Date: 07/22/2004
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Gomez, Ramon A., Tan, Loke, Kuhlmann, Martin
• Granted Patent: US 8,239,914 B2
• Time in Patent Office: Days
• US Class Current: 725/100
• CPC Class Codes: H04N 21/41 Structure of client; Structure of client peripherals
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4383 Accessing a communication channel

Abstract

A highly integrated set-top box is implemented on a single semiconductor substrate. For instance, an analog RF tuner is implemented on the same substrate with a digital receiver, and audio-video back-end circuits. The single chip set-top box can be used for satellite, cable, internet, or terrestrial TV applications, or other applications. As a result, the substrate area, assembly time, and associated costs per chip are reduced.

Claims

1. A set-top box, comprising:

a common substrate;

an analog tuner;

a digital receiver coupled to an output of said analog tuner; and

one or more audio and video back-end circuits coupled to an output of said digital receiver;

said analog tuner, said digital receiver, and said one or more audio and video back-end circuits implemented on said common substrate.

2. The set-top box of claim 1, wherein said analog tuner is a single conversion tuner that down-converts a selected channel from a plurality of channels received at an RF input of said single conversion tuner.

3. The set-top box of claim 2, wherein said digital receiver is a QPSK digital receiver.

4. The set-top box of claim 1, wherein said one or more audio and video backend circuits includes:

a divider module, coupled to said output of said digital receiver, separating a video portion from an audio portion of said output of said digital receiver;

a video module, coupled to said divider module output, for processing said video portion of said output of said digital receiver; and

an audio module, coupled to said divider module output, for processing said audio portion of said output of said digital receiver.

5. The set-top box of claim 4, further comprising a universal serial bus interface disposed on said common substrate, and coupled to said audio and video modules.

6. The set-top box of claim 1, further comprising a DIRECT TV security device disposed on said substrate.

7. The set-top box of claim 1, further comprising an external memory interface disposed on said substrate.

8. The set-top box of claim 7, wherein said external memory interface is a dynamic random access memory (DRAM) interface.

9. The set-top box of claim 1, further comprising a peripheral interface disposed on said substrate.

10. The set-top box of claim 1, wherein said analog tuner is a direct conversion analog tuner.

11. The set-top box of claim 1, wherein an output of said digital receiver includes Moving Picture Experts Group (MPEG) packets, and wherein said one or more audio and video back-end circuits includes a divider module that separates video MPEG packets from audio MPEG packets.

12. The set-top box of claim 11, wherein a video module processes said video MPEG packets to produce a video output, and an audio module processes said audio MPEG packets to produce an audio output.

13. The set-top box of claim 12, wherein said video module includes the following:

a video decoder that decodes said video MPEG packets;

a graphics module, coupled to an output of said video decoder, that adds text to said video MPEG packets;

a video encoder, coupled to an output of said graphics module; and

a video digital-to-analog converter that converts an output of said video encoder to analog.

14. The set-top box of claim 12, wherein said audio module includes:

an MPEG audio decoder that receives and decodes said audio MPEG packets; and

an audio digital-to-analog converter, coupled to an output of said MPEG audio decoder, that converts an output of said MPEG audio decoder to analog.

15. The set-top box of claim 1, wherein said analog tuner includes:

a quadrature down-conversion circuit that produces a quadrature down-converted signal by mixing an RF signal received at an input of said analog tuner with a quadrature local oscillator signal;

an analog-to-digital converter (ADC) coupled to an output of said quadrature down-conversion circuit that digitizes said quadrature down-converted signal; and

a demodulation circuit coupled to an output of said ADC that demodulates said digitized quadrature down-converted signal to produce a data output.

16. The set-top box of claim 15, further comprising a multiplexer coupled between said output of said quadrature down-conversion circuit and an input of said ADC.

17. The set-top box of claim 15, further comprising a de-multiplexer coupled between said output of said ADC and an input of said demodulation circuit.

18. The set-top box of claim 15, further comprising an in-phase/quadrature-phase (IQ) error detection circuit that determines an IQ error of said quadrature down-converted signal.

19. The set-top box of claim 18, further comprising a local oscillator circuit that generates said quadrature local oscillator signal based on an output of said IQ error detection circuit.

20. The set-top box of claim 19, wherein said local oscillator circuit corrects any IQ phase imbalance determined by said IQ error detection circuit.

21. The set-top box of claim 19, wherein said local oscillator circuit includes:

a direct digital frequency synthesizer (DDFS) that produces a digital representation of said quadrature local oscillator signal; and

a pair of digital-to-analog converters (DACs) that are coupled to quadrature outputs of said DDFS.

22. The set-top box of claim 21, wherein said local oscillator circuit includes:

a pair of low pass filters (LPFs) coupled to corresponding outputs of said DACs; and

a phase-Locked Loop (PLL) coupled to said outputs of said pair of DACs, said PLL multiplying a frequency of said outputs of said pair of DACs to produce said quadrature local oscillator signal.

23. The set-top box of claim 15, further comprising an equalizer coupled between said ADC converter and said demodulation circuit, said equalizer performing IQ imbalance correction.

24. The set-top box of claim 23, wherein said equalizer includes a non-decision directed portion that receives an output of said ADC converter and a decision directed portion coupled to an output of said non-decision directed portion.

25. The set-top box of claim 23, wherein said equalizer includes a non-decision directed portion that receives an output of said ADC converter.

26. The set-top box of claim 23, wherein said equalizer includes a decision directed portion that receives an output of said ADC converter.