Integrated set-top box

• US 20060026661A1
• Filed: 05/20/2005
• Published: 02/02/2006
• Est. Priority Date: 05/21/2004
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Gomez, Ramon A., Tan, Loke, McMullin, Donald G., Burns, Lawrence M., Dauphinee, Leonard
• Granted Patent: US 8,732,788 B2
• Time in Patent Office: Days
• US Class Current: 725/127
• CPC Class Codes: H04N 21/40 Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
• CPC Class Codes: H04N 21/6168 involving cable transmission, e.g. using a cable modem
• CPC Class Codes: H04N 7/17309 Transmission or handling of upstream communications

Abstract

The present invention is an integrated set-top box. In one embodiment, the up-stream path and the down-stream path are integrated on a common semiconductor substrate. The down-stream path can include a TV tuner and a digital receiver portion that is integrated on the common semiconductor substrate with a power amplifier of the up-stream path. In another embodiment, the TV tuner is implemented on a first semiconductor substrate and the digital receiver portion and the power amplifier are configured on a second semiconductor substrate. However, the two substrates are mounted on a common carrier so that the set-top box appears to be a single chip configuration to the user.

Claims

1. An integrated set-top box, comprising:

a substrate;

a down-stream path disposed on the substrate for down-converting a radio frequency (RF) signal, including;

a quadrature down-conversion circuit that produces a quadrature down-converted signal by mixing said RF signal with a quadrature local oscillator signal;

an analog-to-digital converter (ADC) coupled to an output of said quadrature down-conversion circuit that digitizes said quadrature down-converted signal; and

a demodulation circuit coupled to an output of said ADC that demodulates said digitized quadrature down-converted signal to produce a data output.

2. The integrated set-top box of claim 1, further comprising a multiplexer coupled between said output of said quadrature down-conversion circuit and an input of said ADC.

3. The integrated set-top box of claim 1, further comprising a demultiplexer coupled between said output of said ADC and an input of said demodulation circuit.

4. The integrated set-top box of claim 1, further comprising an in-phase/quadrature-phase (I/Q) Error Detection circuit that determines an I/Q error of said quadrature down-converted signal.

5. The integrated set-top box of claim 4, further comprising a local oscillator circuit that generates said quadrature local oscillator signal based on an output of said I/Q error detection circuit.

6. The integrated set-top box of claim 5, wherein said local oscillator circuit corrects any I/Q phase imbalance determined by said I/Q error detection circuit.

7. The integrated set-top box of claim 5, wherein said local oscillator circuit includes:

a direct digital frequency synthesizer (DDFS) that produces a digital representation of said quadrature local oscillator signal; and

a pair of digital-to-analog converters (DACs) that are coupled to quadrature outputs of said DDFS.

8. The integrated set-top box of claim 6, wherein said local oscillator circuit includes:

a pair of low pass filters (LPFs) coupled to corresponding outputs of said DACs; and

a Phase-Locked Loop (PLL) coupled to said outputs of said pair of DACs, said PLL multiplying a frequency of said outputs of said pair of DACs to produce said quadrature local oscillator signal.

9. The integrated set-top box of claim 1, wherein said demodulation circuit includes a first digital portion and a second digital portion coupled in parallel to an output of said ADC.

10. The integrated set-top box of claim 9, wherein said first digital portion of said demodulation circuit generates a Motion Picture Expert Group (MPEG) output from said digitized quadrature down-converted signal, and said second digital portion of said demodulation circuit generates an audio and video output from said MPEG output.

11. The integrated set-top box of claim 1, wherein said demodulator circuit includes a first digital portion having at least one of a nyquist filter, a symbol timing circuit, an equalizer, and a MPEG decoder.

12. The integrated set-top box of claim 11, wherein said demodulator circuit includes a second digital portion having a means for encoding and displaying an output of said MPEG decoder.

13. The integrated set-top box of claim 1, further comprising:

an up-stream path disposed on said substrate for producing an up-stream signal.

14. The integrated set-top box of claim 13, wherein said up-stream path includes a power amplifier disposed on said substrate.

15. The integrated set-top box of claim 14, wherein said up-stream path further includes at least one of the following disposed on said substrate:

a DAC converter, a media access controller (MAC), and a control circuit.

19. The set-top box of claim 2, further comprising an equalizer coupled between said A/D converter and said demodulator circuit, said equalizer performing I/Q imbalance correction.

20. The set-top box of claim 19, wherein said equalizer includes a non-decision directed portion that receives an output of said A/D converter and decision directed portion coupled to an output of said non-decision directed portion.

16. A set-top box, comprising:

a common carrier;

a down-stream path having a tuner and a digital receiver portion,

said tuner disposed on a first substrate and attached to said common carrier; and

said digital receiver portion disposed on a second substrate attached to said common carrier; and

an up-stream path having a power amplifier disposed on said second substrate with said digital receiver portion.

17. The set-top box of claim 16, wherein said tuner is a dual conversion tuner having an off-chip surface acoustic wave (SAW) filter that is disposed on said common carrier.

18. The set-top box of claim 16, wherein said digital receiver portion is a quadrature direct down-conversion circuit.