Thin film transistor and method of fabricating the same

• US 20060027805A1
• Filed: 08/01/2005
• Published: 02/09/2006
• Est. Priority Date: 08/07/2004
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung SDI Company Limited
• Inventors: Suh, Min-Chul, Koo, Jae-Bon
• Granted Patent: US 7,348,593 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/31691 with perovskite structure
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/468 characterised by the gate dielectrics
• CPC Class Codes: H10K 71/60 Forming conductive regions or layers, e.g. electrodes
• CPC Class Codes: H10K 77/111 Flexible substrates
• CPC Class Codes: H10K 85/10 Organic polymers or oligomers
• CPC Class Codes: H10K 85/111 comprising aromatic, heteroaromatic, or aryl chains, e.g. polyaniline, polyphenylene or polyphenylene vinylene
• CPC Class Codes: H10K 85/113 Heteroaromatic compounds comprising sulfur or selene, e.g. polythiophene
• CPC Class Codes: H10K 85/1135 Polyethylene dioxythiophene [PEDOT]; Derivatives thereof
• CPC Class Codes: H10K 85/615 Polycyclic condensed aromatic hydrocarbons, e.g. anthracene
• CPC Class Codes: H10K 85/621 Aromatic anhydride or imide compounds, e.g. perylene tetra-carboxylic dianhydride or perylene tetracarboxylic di-imide
• CPC Class Codes: Y02E 10/549 Organic PV cells

Abstract

An organic thin film transistor (OTFT) having an adhesive layer and a method of fabricating the same. The OTFT includes a gate electrode formed on a substrate, a gate insulating layer formed on the gate electrode and on remaining exposed portions of the substrate, an adhesive layer formed on the gate insulating layer, source/drain electrodes formed on the adhesive layer, and a semiconductor layer formed on the source/drain electrodes and on the adhesive layer. The gate insulating layer and the semiconductor layer are organic, the adhesive layer providing adhesion between the source/drain electrodes and the gate insulating film while preventing gate leakage current while also improving contact resistance.

Claims

1. A thin film transistor (TFT), comprising:

a gate electrode arranged on a substrate;

a gate insulating layer arranged on the gate electrode and on exposed portions of the substrate;

an adhesive layer arranged on the gate insulating layer;

source/drain electrodes arranged on the adhesive layer, an exposed portion of the adhesive layer remaining between the source electrode and the drain electrode; and

a semiconductor layer arranged on the source/drain electrodes and on the exposed portion of the adhesive layer.

2. The TFT of claim 1, the semiconductor layer comprises an organic semiconductor material, the gate insulating layer comprises an organic insulating layer that includes a substance selected from the group consisting of benzocyclobutene (BCB), polyimide and parylene.

3. The TFT of claim 1, the adhesive layer comprises an oxide of a second metal, the second metal being selected from the group consisting of Ti, Cr, Mo and Al.

4. The TFT of claim 1, each of the source/drain electrodes comprises:

an electrode layer; and

a binding layer arranged between the electrode layer and the adhesive layer.

5. The TFT of claim 4, the electrode layer comprises a first metal selected from the group consisting of Au, Ni, Pt, Pd, Os, Rh, Ru and Ir.

6. The TFT of claim 5, the adhesive layer comprises an oxide of a second metal, the second metal having a lower work function than the first metal.

7. The TFT of claim 6, the second metal being selected from the group consisting of Ti, Cr, Mo and Al.

8. The TFT of claim 4, the binding layer comprises a third metal selected from the group consisting of Ti, Cr, Mo and Al.

9. The TFT of claim 1, each of the source/drain electrodes comprises an electrode layer, the electrode layer being a first metal selected from the group consisting of Au, Ni, Pt, Pd, Os, Rh, Ru and Ir.

10. The TFT of claim 9, the adhesive layer comprises an oxide of a second metal, the second metal having a lower work function than the first metal.

11. The TFT of claim 10, the second metal being selected from the group consisting of Ti, Cr, Mo and Al.

12. A flat panel display, comprising at least one thin film transistor (TFT) arranged on a substrate, the TFT including a gate electrode, source/drain electrodes, a semiconductor layer and an insulating layer, the insulating layer being arranged between the gate electrode and the source/drain electrodes, each of the source/drain electrodes comprise an electrode layer, the electrode layer being of a first metal, the first metal being a noble metal, the semiconductor layer being of an organic semiconductor material, the insulating layer being a metal oxide and adapted to function simultaneously as a gate insulating layer for the TFT and as an adhesive layer that increases adhesion between the source/drain electrodes and the insulating layer.

13. The flat panel display of claim 12, the source/drain electrodes further comprises a binding layer arranged underneath the electrode layer, the binding layer comprising a second metal that is oxidizable, the second metal having a lower work function than the first metal, the insulating layer comprises an oxide of the second metal.

14. The flat panel display of claim 13, the first metal being selected from the group consisting of Pt, Au, Pd, Ni, Rh, Ru, Ir and Os, the second metal being selected from the group consisting of Ti, Cr, Mo and Al.

15. A method of fabricating a TFT, comprising:

forming a gate electrode on a substrate;

forming a gate insulating layer on the gate electrode and on exposed portions of the substrate;

forming an adhesive layer on the gate insulating layer;

forming a source electrode and a drain electrode on the adhesive layer; and

forming a semiconductor layer on the source electrode, the drain electrode and on exposed portions of the adhesive layer between the source electrode and the drain electrode.

16. The method of claim 15, the forming of the adhesive layer and the forming of the source electrode and the drain electrode comprises:

forming a first insulating layer on the gate insulating layer;

depositing a first metal layer on the first insulating layer; and

etching the first metal layer and the first insulating layer to form the source electrode, the drain electrode and the adhesive layer.

17. The method of claim 16, the source electrode and the drain electrode each comprise an electrode layer, the electrode layer being a first metal and a binding layer arranged between the electrode layer and the gate insulating layer, the binding layer adapted to increase adhesion between the electrode layer and the gate insulating layer.

18. The method of claim 17, the binding layer comprises a second metal, the second metal being selected from the group consisting of Ti, Cr, Mo and Al.

19. The method of claim 17, the first insulating layer comprises an oxide of a third metal, the third metal being selected from the group consisting of Ti, Cr, Mo and Al.

20. The method of claim 16, the etching of the first insulating layer occurring simultaneously with the etching of the first metal layer, the etching using a half tone mask.

21. The method of claim 16, the etching of the first insulating layer occurring before the depositing of the first metal layer, the first metal layer being etched in a second and subsequent etch step separate from the etching of the first insulating layer.