Semiconductor device

• US 20060028868A1
• Filed: 08/08/2005
• Published: 02/09/2006
• Est. Priority Date: 08/09/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Matsui, Toshikazu, Nitta, Kyoya, Okazaki, Tsutomu, Hisamoto, Digh, Tanaka, Toshihiro, Okada, Daisuke, Yasui, Kan, Ishii, Yasushi, Kato, Akira
• Granted Patent: US 7,245,531 B2
• Time in Patent Office: Days
• US Class Current: 365/185.50
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween. The memory gate line has a contact section that extends in the X direction from over a second portion of the select gate line to over an element isolation region, and is connected to its corresponding wiring through a plug that buries a contact hole formed over the contact section.

Claims

1. A semiconductor device comprising:

memory cells arranged in plural array form, said each memory cell including;

(a) a drain region and a source region formed in a semiconductor substrate;

(b) a first gate electrode and a second gate electrode formed over said semiconductor substrate above between said drain region and said source region, said first gate electrode being positioned on said drain region side and said second gate electrode being positioned on said source region side and adjacent to said first gate electrode with a first insulating film interposed therebetween;

(c) a first gate insulating film formed between said first gate electrode and said semiconductor substrate; and

(d) a second gate insulating film formed between said second gate electrode and said semiconductor substrate, said second gate insulating film having a charge storage section thereinside,

wherein a plurality of first gate lines connected to said first gate electrodes of said memory cells arranged in a first direction, of said plurality of memory cells, and a plurality of second gate lines being adjacent to said first gate lines through a second insulating film interposed therebetween and connected to said second gate electrodes of said memory cells arranged in said first direction, of said plurality of memory cells, are provided, and

wherein said second gate lines respectively connected to said second gate electrodes of said memory cells adjacent to one another in a second direction intersecting said first direction with said source regions interposed therebetween are not electrically connected to one another, and voltages are capable of being applied thereto independently.

2. The semiconductor device according to claim 1, wherein upon an operation of writing into a selected memory cell of said plurality of memory cells, different voltages are respectively supplied to said second gate line connected to said second gate electrode of said selected memory cell, and said second gate line connected to said second gate electrode of a non-selected memory cell adjacent to said selected memory cell in said second direction through said source region interposed therebetween.

3. A semiconductor device comprising:

memory cells arranged in plural array form, said each memory cell including;

(a) a first semiconductor region formed in a semiconductor substrate and serving as one of a drain region and a source region, and a second semiconductor region serving as the other thereof;

(b) a first gate electrode and a second gate electrode formed over said semiconductor substrate above between said first semiconductor region and said second semiconductor region, said first gate electrode being positioned on said first semiconductor region side and said second gate electrode being positioned on said second semiconductor region side and adjacent to said first gate electrode with a first insulating film interposed therebetween;

(c) a first gate insulating film formed between said first gate electrode and said semiconductor substrate; and

(d) a second gate insulating film formed between said second gate electrode and said semiconductor substrate, said second gate insulating film having a charge storage section thereinside,

wherein a plurality of first gate lines connected to said first gate electrodes of said memory cells arranged in a first direction, of said plurality of memory cells, and a plurality of second gate lines being adjacent to said first gate lines through a second insulating film interposed therebetween and connected to said second gate electrodes of said memory cells arranged in said first direction, of said plurality of memory cells, are provided,

wherein an interlayer insulating film is formed over said semiconductor substrate so as to cover said first and second gate electrodes and said first and second gate lines,

wherein each of said first gate lines has a first portion extending in said first direction and a second portion having one end connected to said first portion and extending in a second direction intersecting said first direction, wherein each of said second gate lines has a third portion adjacent to said first and second portions of said first gate line with said second insulating film interposed therebetween, and a fourth portion being adjacent to said second portion of said first gate line with said second insulating film interposed therebetween and extends in a third direction intersecting said second direction, and

wherein a first contact hole is defined in an interlayer insulating film provided over said fourth portion of each of said second gate lines, and a first conductor section embedded in said first contact hole and said fourth portion of said second gate line are electrically connected to each other.

4. The semiconductor device according to claim 3, wherein said second direction is a direction orthogonal to said first direction.

5. The semiconductor device according to claim 3, wherein said third direction is parallel to said first direction.

6. The semiconductor device according to claim 3, wherein said first gate lines and said first gate electrodes respectively comprise a first conductor layer of the same layer, and said second gate lines and said second gate electrodes respectively comprise a second conductor layer of the same layer.

7. The semiconductor device according to claim 3,

wherein each of said second gate electrodes is formed over sidewalls of said first gate electrode in sidewall form through said first insulating film interposed therebetween, and

wherein said third portion of each of said second gate lines is formed over sidewalls of said first and second portions of said first gate line in sidewall form with said second insulating film interposed therebetween.

8. The semiconductor device according to claim 3, wherein said first insulating film and said second insulating film are respectively constituted of an insulating film identical in layer to said second gate insulating film.

9. The semiconductor device according to claim 3,

wherein said semiconductor substrate has element isolation regions each comprised of an insulator, and

wherein said fourth portion of each of said second gate lines extends in said third direction from over said second portion of each of said first gate lines to over the corresponding element isolation region.

10. The semiconductor device according to claim 9, wherein said first contact hole is formed in said interlayer insulating film provided over said fourth portion located over said element isolation region.

11. The semiconductor device according to claim 3, including:

a first wiring formed over said interlayer insulating film and electrically connected to said fourth portion of each of said second gate lines through said first conductor section embedded in said first contact hole.

12. The semiconductor device according to claim 11, wherein said first wiring extends in a direction orthogonal to said first direction.

13. The semiconductor device according to claim 3, wherein said first semiconductor region serves as said drain region, and said second semiconductor region serves as the source region.

14. The semiconductor device according to claim 13, wherein said second gate lines respectively connected to said second gate electrodes of said memory cells adjacent to one another in a fourth direction intersecting said first direction through said second semiconductor region interposed therebetween are electrically connected to one another.

15. The semiconductor device according to claim 14, wherein upon an operation of writing into a selected memory cell of said plurality of memory cells, different voltages are respectively supplied to said second gate line connected to said second gate electrode of said selected memory cell, and said second gate line connected to said second gate electrode of a non-selected memory cell adjacent to said selected memory cell in said fourth direction through said source region interposed therebetween.

16. The semiconductor device according to claim 13, wherein said second gate lines respectively connected to said second gate electrodes of said memory cells adjacent to one another in said fourth direction through said second semiconductor region are respectively shifted in said first direction in terms of connecting positions of said fourth portions and said first conductor sections and electrically connected to different wirings formed over said interlayer insulating film.

17. The semiconductor device according to claim 13, further including a plurality of memory cell array forming regions formed with a plurality of said memory cells in array form,

wherein element isolation regions each formed of an insulator are formed among said plurality of memory cell forming regions, and

wherein said first and second gate lines extend over said element isolation regions among said memory cell forming regions.

18. The semiconductor device according to claim 17, wherein a second contact hole is defined in said interlayer insulating film provided over said second semiconductor region at an outer peripheral portion of each of said memory cell array forming regions, and a second conductor section embedded in said second contact hole and said corresponding second semiconductor region are electrically connected to each other.

19. A semiconductor device comprising:

memory cells arranged in plural array form, said each memory cell including;

(a) a drain region and a source region formed in a semiconductor substrate;

(b) a first gate electrode and a second gate electrode formed over said semiconductor substrate above between said drain region and said source region, said first gate electrode being positioned on said drain region side, and said second gate electrode being positioned on said source region side and formed over sidewalls of said first gate electrode in sidewall form with a first insulating film interposed therebetween;

(c) a first gate insulating film formed between said first gate electrode and said semiconductor substrate; and

(d) a second gate insulating film formed between said second gate electrode and said semiconductor substrate and comprising an insulating film identical in layer to said first insulating film, said second gate insulating film having a charge storage section thereinside,

wherein a plurality of first gate lines connected to said first gate electrodes of said memory cells arranged in a first direction, of said plurality of memory cells and each comprising a first conductor layer identical in layer to said first gate electrode, and a plurality of second gate lines being adjacent to said first gate lines through a second insulating film identical in layer to said first insulating film and connected to said second gate electrodes of said memory cells arranged in said first direction, of said plurality of memory cells, and each comprising a second conductor layer identical in layer to said second gate electrode, are provided,

wherein an interlayer insulating film is formed over said semiconductor substrate so as to cover said first and second gate electrodes and said first and second gate lines,

wherein each of said first gate lines has a first portion extending in said first direction and a second portion of which one end is connected to said first portion and which extends in a second direction orthogonal to said first direction,

wherein each of said second gate lines has a third portion formed over sidewalls of said first and second portions of each of said first gate line in sidewall form with said second insulating film interposed therebetween, and a fourth portion being adjacent to said second portion of said first gate line with said second insulating film interposed therebetween and extends in said first direction, and

wherein a first contact hole is defined in said interlayer insulating film provided over said fourth portion of each of said second gate lines, and a first conductor section embedded in said first contact hole and said fourth portion of said second gate line are electrically connected to each other.

20. The semiconductor device according to claim 19, further including a plurality of first wirings each formed over said interlayer insulating film so as to extend in said second direction and electrically connected to said fourth portion of each of said second gate lines through said first conductor section embedded in said first contact hole,

wherein said second gate lines respectively connected to said second gate electrodes of said memory cells adjacent to one another in said second direction through said source region interposed therebetween are not electrically connected to one another and are electrically connected to said first wirings respectively different from one another.

21. A semiconductor device comprising:

at least two memory cells connected to a common source line and disposed adjacent to each other so as to be opposite to a source line,

wherein upon an operation of writing into said memory cells, a value of a voltage applied to a word line of a selected memory cell on which writing is effected, of said two memory cells is different from a value of a voltage applied to a word line of a non-selected memory cell thereof on which no writing is effected.

22. The semiconductor device according to claim 21, wherein said value of said voltage applied to said word line of said selected memory cell is larger than said value of said voltage applied to said word line of said non-selected memory cell.