Different numbers of bits per cell in non-volatile memory devices

• US 20060028877A1
• Filed: 01/19/2005
• Published: 02/09/2006
• Est. Priority Date: 08/05/2004
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: M-Systems Flash Disk Pioneers Ltd. (Western Digital Corporation)
• Inventors: Meir, Avraham
• Granted Patent: US 7,180,775 B2
• Time in Patent Office: Days
• US Class Current: 365/185.330
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A method of manufacturing a non-volatile flash memory device, including setting a first number of bits stored per cell for at least one first cell less than a second number of bits stored per cell for at least one second cell such that the setting permanently fixes the first number and the second number prior to shipping the device for use. Preferably the setting is based on predicted reliabilities of the cells. Preferably, the predicted reliability of the first cells is less than the predicted reliability of the second cells. Preferably, the setting is based on respective locations within the device of the first cells and the second cells. Preferably, the setting is based on respective word lines connecting to the first cells and the second cells

Claims

1. A method of manufacturing a non-volatile flash memory device, the method comprising the step of:

(a) setting a first number of bits stored per cell for at least one first cell less than a second number of bits stored per cell for at least one second cell;

wherein said setting permanently fixes said first number and said second number prior to shipping the device for use.

2. The method, according to claim 1, wherein said setting is based on respective predicted reliabilities of said at least one first cell and said at least one second cell.

3. The method, according to claim 2, wherein said predicted reliability of said at least one first cell is less than said predicted reliability of said at least one second cell.

4. The method, according to claim 1, wherein said setting is based on respective locations within the device of said at least one first cell and said at least one second cell.

5. The method, according to claim 1, wherein said setting is based on respective word lines connecting to said at least one first cell and said at least one second cell.

6. A non-volatile flash memory device, wherein during manufacture of the device, a first number of bits stored per cell of at least one first cell is set less than a second number of bits stored per cell of at least one second cell;

wherein said device comprises a mechanism which permanently fixes said first number and said second number prior to shipping the device for use.

7. The device, according to claim 6, wherein said first number and said second are based on respective predicted reliabilities of said at least one first cell and said at least one second cell.

8. The device, according to claim 7, wherein said predicted reliability of said at least one first cell is less than said predicted reliability of said at least one second cell.

9. The device, according to claim 6, wherein said first number and said second number are based on respective locations within the device of said at least one first cell and said at least one second cell.

10. The device, according to claim 6, wherein said first number and said second number are based on word lines connecting respectively to said at least one first cell and said at least one second cell.

11. A system for manufacturing a non-volatile flash memory device, the system comprising:

(a) the flash memory device including at least one first cell and at least one second cell; and

(b) a mechanism for setting a first number of bits stored per cell of said at least one first cell less than a second number of bits stored per cell of said at least one second cell;

wherein the device includes a mechanism which permanently fixes said first number and said second number prior to shipping the device for use.

12. The system, according to claim 11, wherein said first number and said second are based on respective predicted reliabilities of said at least one first cell and said at least one second cell.

13. The system, according to claim 12, wherein said predicted reliability of said at least one first cell is less than said predicted reliability of said at least one second cell.

14. The system, according to claim 11, wherein said first number and said second number are based on respective locations within the device of said at least one first cell and said at least one second cell.

15. The system, according to claim 11, wherein said first number and said second number are based on word lines connecting respectively to said at least one first cell and said at least one second cell.