Integrated circuit devices including passive device shielding structures and methods of forming the same

• US 20060030115A1
• Filed: 01/25/2005
• Published: 02/09/2006
• Est. Priority Date: 08/03/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chung, Chulho
• Granted Patent: US 7,663,205 B2
• Time in Patent Office: Days
• US Class Current: 438/381
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Integrated circuit devices include a semiconductor substrate and a flux line generating passive electronic element on the semiconductor substrate. A dummy gate structure is arranged on the semiconductor substrate in a region below the passive electronic element. The dummy gate includes a plurality of segments, each segment including a first longitudinally extending part and a second longitudinally extending part. The second longitudinally extending part extends at an angle from an end of the first longitudinally extending part. Ones of the segments extend at a substantially same angle and are arranged displaced from each other in an adjacent nested relationship.

Claims

1. An integrated circuit device comprising:

a semiconductor substrate;

a flux line generating passive electronic element on the semiconductor substrate;

a dummy gate structure arranged on the semiconductor substrate in a region below the passive electronic element, the dummy gate comprising a plurality of segments, each segment including a first longitudinally extending part and a second longitudinally extending part, the second longitudinally extending part extending at an angle from an end of the first longitudinally extending part and wherein ones of the segments extend at a substantially same angle and are arranged displaced from each other in an adjacent nested relationship.

2. The integrated circuit device of claim 1 wherein the dummy gate structure is configured to inhibit penetration into the semiconductor substrate of flux lines generated by the passive electronic element.

3. The integrated circuit device of claim 2 wherein the passive electronic element comprises an inductor and wherein at least half of the segments extend in a direction orthogonal to a corresponding overlying portion of the inductor.

4. The integrated circuit device of claim 2 further comprising a plurality of isolation regions in the region below the passive electronic element and wherein the dummy gate structure segments are positioned on the isolation regions to define a first shield.

5. The integrated circuit device of claim 4 further comprising a plurality of conductive regions between the isolation regions configured to define a complementary second shield.

6. The integrated circuit device of claim 5 wherein the plurality of conductive regions comprise a metal silicide pattern on the semiconductor substrate.

7. The integrated circuit device of claim 5 further comprising an interlayer dielectric layer on the semiconductor substrate extending over the dummy gate structure and the plurality of conductive regions and wherein the passive electronic element is positioned on the interlayer dielectric layer.

8. The integrated circuit device of claim 7 further comprising a conductive screen extending into the interlayer dielectric region around the passive electronic element and defining a perimeter surrounding the passive electronic element, the conductive screen being configured to limit penetration of flux lines generated by the passive electronic element past the perimeter.

9. The integrated circuit device of claim 8 wherein the conductive screen comprises a plurality of columns of conductive elements extending into the interlayer dielectric layer along the perimeter, the columns being displaced from each other and each of the columns including a plurality of electrically coupled conductive elements displaced from each other.

10. The integrated circuit device of claim 9 wherein the passive element comprises an inductor.

11. The integrated circuit device of claim 10 wherein the region below the passive electronic element comprises a passive region of the integrated circuit device, the integrated circuit device further comprising an active region on the semiconductor substrate proximate to the passive region and outside the perimeter, the active region including active device gate electrodes formed while forming the plurality of dummy gate electrodes.

12. The integrated circuit device of claim 10 wherein the region below the passive electronic element comprises a passive region of the integrated circuit device, the integrated circuit device further comprising an active region on the semiconductor substrate proximate to the passive region and outside the perimeter, the active region including active device gate electrodes formed on a same layer of the integrated circuit device as the dummy gate structure.

13. The integrated circuit device of claim 9 further comprising a complementary conductive screen extending into the interlayer dielectric region around the passive electronic element and defining a second perimeter surrounding the passive electronic element adjacent and displaced from the first conductive screen, the complementary conductive screen being configured to limit penetration of flux lines generated by the passive electronic element past the perimeter, wherein the complementary conductive screen has a plurality of columns aligned with spaces between columns of the first conductive screen.

14. The method of claim 7 wherein the dummy gate structure comprises a gate insulating layer on the semiconductor substrate and a conductive gate electrode on the gate insulating layer.

15. The method of claim 14 wherein the dummy gate structure further comprise a silicide layer on the gate electrode and insulative sidewalls on sides of the gate insulating layer, gate electrode and silicide layer.

16. The integrated circuit device of claim 7 wherein the interlayer dielectric layer comprises a first and a second interlayer dielectric layer and wherein the first interlayer dielectric region is formed on the dummy gate electrode and the plurality of conductive regions are formed on the first interlayer dielectric layer and wherein the second interlayer dielectric layer is formed on the plurality of conductive regions.

17. The integrated circuit device of claim 16 wherein the passive electronic element comprises a capacitor.

18. The integrated circuit device of claim 5 further comprising a metal contact coupled to the dummy gate structure in a central region thereof under the passive electronic element, the metal contact connecting the dummy gate structure to ground.

19. The integrated circuit device of claim 18 further comprising a metal contact coupled to the plurality of conductive regions in a central region thereof under the passive electronic element, the metal contact to the plurality of conductive regions connecting the plurality of conductive regions to ground.

20. The integrated circuit device of claim 2 further comprising a metal contact coupled to the dummy gate structure in a central region thereof under the passive electronic element, the metal contact connecting the dummy gate structure to ground.

21. The integrated circuit device of claim 2 wherein the dummy gate structure comprises a plurality of sets of the segments arranged in a symmetrical pattern.

22. An integrated circuit device comprising:

a semiconductor substrate;

a flux line generating passive electronic element on the semiconductor substrate;

a dummy gate structure arranged on the semiconductor substrate in a region below the passive electronic element, the dummy gate structure being arranged to inhibit penetration into the semiconductor substrate of flux lines generated by the passive electronic element; and

a metal contact coupled to the dummy gate structure in a central region thereof under the passive electronic element, the metal contact connecting the dummy gate structure to ground.

23. The integrated circuit device of claim 22 wherein the passive electronic element comprises an inductor and wherein the dummy gate structure includes a plurality of longitudinally extending segments, at least half of the segments extending in a direction orthogonal to a corresponding overlying portion of the inductor.

24. The integrated circuit device of claim 22 further comprising a plurality of isolation regions in the region below the passive electronic element and wherein the dummy gate structure segments are positioned on the isolation regions to define a first shield.

25. The integrated circuit device of claim 24 further comprising a plurality of conductive regions between the isolation regions configured to define a complementary second shield.

26. The integrated circuit device of claim 25 wherein the plurality of conductive regions comprise a metal silicide pattern on the semiconductor substrate.

27. The integrated circuit device of claim 25 further comprising an interlayer dielectric layer on the semiconductor substrate extending over the dummy gate structure and the plurality of conductive regions and wherein the passive electronic element is positioned on the interlayer dielectric layer.

28. The integrated circuit device of claim 27 further comprising a conductive screen extending into the interlayer dielectric region around the passive electronic element and defining a perimeter surrounding the passive electronic element, the conductive screen being configured to limit penetration of flux lines generated by the passive electronic element past the perimeter.

29. The integrated circuit device of claim 28 wherein the conductive screen comprises a plurality of columns of conductive elements extending into the interlayer dielectric layer along the perimeter, the columns being displaced from each other and each of the columns including a plurality of electrically coupled conductive elements displaced from each other.

30. The integrated circuit device of claim 29 wherein the passive element comprises an inductor.

31. The integrated circuit device of claim 30 wherein the region below the passive electronic element comprises a passive region of the integrated circuit device, the integrated circuit device further comprising an active region on the semiconductor substrate proximate to the passive region and outside the perimeter, the active region including active device gate electrodes formed while forming the plurality of dummy gate electrodes.

32. The integrated circuit device of claim 30 wherein the region below the passive electronic element comprises a passive region of the integrated circuit device, the integrated circuit device further comprising an active region on the semiconductor substrate proximate to the passive region and outside the perimeter, the active region including active device gate electrodes formed on a same layer of the integrated circuit device as the dummy gate structure.

33. The integrated circuit device of claim 29 further comprising a complementary conductive screen extending into the interlayer dielectric region around the passive electronic element and defining a second perimeter surrounding the passive electronic element adjacent and displaced from the first conductive screen, the complementary conductive screen being configured to limit penetration of flux lines generated by the passive electronic element past the perimeter, wherein the complementary conductive screen has a plurality of columns aligned with spaces between columns of the first conductive screen.

34. The method of claim 27 wherein the dummy gate structure comprises a gate insulating layer on the semiconductor substrate and a conductive gate electrode on the gate insulating layer.

35. The integrated circuit device of claim 27 wherein the interlayer dielectric layer comprises a first and a second interlayer dielectric layer and wherein the first interlayer dielectric region is formed on the dummy gate electrode and the plurality of conductive regions are formed on the first interlayer dielectric layer and wherein the second interlayer dielectric layer is formed on the plurality of conductive regions.

36. The integrated circuit device of claim 35 wherein the passive electronic element comprises a capacitor.

37. The integrated circuit device of claim 26 further comprising a metal contact coupled to the plurality of conductive regions in a central region thereof under the passive electronic element, the metal contact to the plurality of conductive regions connecting the plurality of conductive regions to ground.

38. The integrated circuit device of claim 22 wherein the dummy gate structure comprises a plurality of sets of the segments arranged in a symmetrical pattern.

39. An integrated circuit device, comprising:

a semiconductor substrate;

a first interlayer dielectric layer on the semiconductor substrate;

a second interlayer dielectric layer on the first interlayer dielectric layer;

a third interlayer dielectric layer on the second interlayer dielectric layer;

a flux line generating passive electronic element on the third interlayer dielectric layer;

a first grounded conductive shield pattern on the first interlayer dielectric layer in a region below the passive electronic element; and

a second grounded conductive shield pattern on the second interlayer dielectric layer in the region below the passive electronic element.

40. The integrated circuit device of claim 39 wherein the first and second grounded conductive shield comprise metal.

41. An integrated circuit device comprising:

a semiconductor substrate;

a flux line generating passive electronic element on the semiconductor substrate;

an isolation region having a plurality of segments in the semiconductor substrate below the passive electronic element defining a first shield pattern that is configured to inhibit penetration into the semiconductor substrate of flux lines generated by the passive electronic element; and

a plurality of conductive elements positioned between ones of the isolation regions to define a complementary second conductive shield pattern that is configured to inhibit penetration into the semiconductor substrate of flux lines generated by the passive electronic element.

42. The integrated circuit device of claim 41 wherein the plurality of conductive elements comprise a dummy gate structure.

43. The integrated circuit device of claim 41 wherein the plurality of conductive elements comprise a metal silicide pattern.

44. An integrated circuit device comprising:

a semiconductor substrate;

a flux line generating capacitor on the semiconductor substrate; and

a dummy gate structure arranged on the semiconductor substrate in a region below the passive electronic element, the dummy gate structure being arranged to inhibit penetration into the semiconductor substrate of flux lines generated by the capacitor.

45. A method of forming an integrated circuit device, comprising:

forming an active device and a passive device region in a semiconductor substrate;

concurrently forming a gate electrode of an active device in the active device region and a dummy gate electrode in the passive device region;

forming a first interlayer dielectric layer on the gate electrode and the dummy gate electrode;

forming a metal plug extending through the first interlayer dielectric layer and contacting the dummy gate electrode at a central region thereof;

forming a metal layer pattern contacting the metal plug to connect the dummy gate electrode to ground;

forming a second interlayer dielectric layer on the metal layer pattern; and

forming a flux line generating passive electronic element on the interlayer dielectric layer over the dummy gate electrode.

46. A method of forming an integrated circuit device, comprising:

forming an active device and a passive device region in a semiconductor substrate;

concurrently forming a gate electrode of an active device in the active device region and a dummy gate electrode structure on the passive device region, the dummy gate electrode structure comprising a plurality of segments, each segment including a first longitudinally extending part and a second longitudinally extending part, the second longitudinally extending part extending at an angle from an end of the first longitudinally extending part and wherein ones of the segments extend at a substantially same angle and are arranged displaced from each other in an adjacent nested relationship;

forming an interlayer dielectric layer on the gate electrode and the dummy gate electrode structure; and

forming a flux line generating passive electronic element on the interlayer dielectric layer over the dummy gate electrode structure.

47. An integrated circuit device comprising:

a semiconductor substrate;

a flux line generating passive electronic element on the semiconductor substrate;

a three dimensional electromagnetic shield disposed around the passive electronic element and between the passive electronic element and the semiconductor substrate, the electromagnetic shield being configured to inhibit penetration into the semiconductor substrate of flux lines emanating from the passive electronic element and to inhibit escape of flux lines emanating from the passive electronic element from a perimeter surrounding the passive electronic element.

48. The integrated circuit device of claim 47 wherein the three dimensional electromagnetic shield comprises a dummy gate structure arranged on the semiconductor substrate in a region below the passive electronic element.

49. The integrated circuit device of claim 48 the dummy gate structure includes a plurality of longitudinally extending segments.

50. The integrated circuit device of claim 49 further comprising a plurality of isolation regions in the semiconductor substrate and wherein the dummy gate structure segments are positioned on the isolation regions to define a first shield.

51. The integrated circuit device of claim 50 wherein the three dimensional electromagnetic shield further comprises a plurality of conductive regions between the isolation regions configured to define a complementary second shield.

52. The integrated circuit device of claim 51 wherein the plurality of conductive regions comprise a metal silicide pattern on the semiconductor substrate.

53. The integrated circuit device of claim 52 further comprising an interlayer dielectric layer on the semiconductor substrate extending over the dummy gate structure and the plurality of conductive regions and wherein the passive electronic element is positioned on the interlayer dielectric layer.

54. The integrated circuit device of claim 53 wherein the three dimensional electromagnetic shield further comprises a conductive screen extending into the interlayer dielectric region around the passive electronic element and defining a perimeter surrounding the passive electronic element, the conductive screen being configured to limit penetration of flux lines generated by the passive electronic element past the perimeter.

55. The integrated circuit device of claim 54 wherein the conductive screen comprises a plurality of columns of conductive elements extending into the interlayer dielectric layer along the perimeter, the columns being displaced from each other and each of the columns including a plurality of electrically coupled conductive elements displaced from each other.

56. The integrated circuit device of claim 50 further comprising a metal contact coupled to the dummy gate structure in a central region thereof under the passive electronic element, the metal contact connecting the dummy gate structure to ground.

57. An integrated circuit device comprising:

a semiconductor substrate;

a flux line generating passive electronic element on the semiconductor substrate;

a plurality of dummy gate structures arranged on the semiconductor substrate in a region below the passive electronic element, the plurality of dummy gate structures being displaced from each other and being arranged to inhibit penetration into the semiconductor substrate of flux lines generated by the passive electronic element.

58. The integrated circuit device of claim 57 further comprising:

an interlayer dielectric layer on the plurality of dummy gate structures;

a metal layer coupled to ground on the interlayer dielectric layer; and

a plurality of conductive contacts extending from the metal layer to the plurality of dummy gate structures to couple the plurality of dummy gate structures to ground through the metal layer.

59. The integrated circuit substrate of claim 58 further comprising a second interlayer dielectric layer on the interlayer dielectric layer on the plurality of gate structures, the second interlayer dielectric layer extending over the plurality of dummy gate structures and wherein the passive electronic element is positioned on the second interlayer dielectric layer.

60. The integrated circuit device of claim 59 further comprising a plurality of isolation regions in the region below the passive electronic element and wherein the dummy gate structures are positioned on the isolation regions to define a first shield.

61. The integrated circuit device of claim 60 further comprising a plurality of conductive regions between the isolation regions configured to define a complementary second shield.

62. The integrated circuit device of claim 61 further comprising a conductive screen extending into the interlayer dielectric layers and defining a perimeter surrounding the passive electronic element, the conductive screen being configured to limit penetration of flux lines generated by the passive electronic element past the perimeter.

63. The integrated circuit device of claim 62 wherein the conductive screen comprises a plurality of columns of conductive elements extending into the interlayer dielectric layers along the perimeter, the columns being displaced from each other and each of the columns including a plurality of electrically coupled conductive elements displaced from each other.

64. The integrated circuit device of claim 61 wherein the plurality of dummy gates comprises a first longitudinally extending part and a second longitudinally extending part, the second longitudinally extending part extending at an angle from an end of the first part and wherein the ones of the dummy gate regions extend at a same angle and are arranged in adjacent nested relationship with the conductive regions therebetween.

65. The integrated circuit device of claim 64 wherein the plurality of dummy gates comprises a plurality of sets of the ones of the plurality of dummy gates arranged in a symmetrical pattern.

66. The integrated circuit device of claim 61 further comprising a metal contact coupled to the plurality of dummy gates in a central region thereof under the passive electronic element, the metal contact connecting the plurality of dummy gates to ground.

67. An integrated circuit device, comprising:

a semiconductor substrate;

a first interlayer dielectric layer on the semiconductor substrate;

a second interlayer dielectric layer on the first interlayer dielectric layer;

a third interlayer dielectric layer on the second interlayer dielectric layer;

a flux line generating passive electronic element on the third interlayer dielectric layer;

a first metal conductive shield pattern on the first interlayer dielectric layer in a region below the passive electronic element; and

a second metal conductive shield pattern on the second interlayer dielectric layer in the region below the passive electronic element.