Layout method for semiconductor integrated circuit device

• US 20060030138A1
• Filed: 08/05/2005
• Published: 02/09/2006
• Est. Priority Date: 08/09/2004
• Status: Abandoned Application

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Konishi, Masashi
• Application Number:
  US11/197,307
• Publication Number:
  US 20060030138A1
• Time in Patent Office: Days
• US Class Current: 438/599
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

Provided is a layout method for a semiconductor integrated circuit device in which area pads and peripheral wiring patterns thereof can be automatically laid out. At least one of a plurality of cells are made area pad cells, at least one of the remaining cells are made wiring pattern cells, and then the area pad cells and the wiring pattern cells are stored in a design library. Arrangement positions of the area pad cells and the wiring pattern cells are calculated based on the design library and prepared arrangement information or wiring structure information on both cells and then both cells are arranged automatically. As a result, a layout design to satisfy design rules can be prepared while securing connections between the cells and between the cells and other wiring patterns through the use of pins and contacts at boundary portions of the cells and intra-cell wiring portions. And at the same time, a layout database having information on all of the layout is created by conducting a conventional automatic layout.

Claims

1. A layout method for a semiconductor integrated circuit device using a design library having information on a plurality of cells, wherein

at least one of the cells are made wiring pattern cells,

the wiring pattern cells are stored in the design library,

arrangement positions of the wiring pattern cells are calculated based on the design library and prepared arrangement information or wiring structure information on the wiring pattern cells, and

the wiring pattern cells are arranged automatically.

2. The layout method for a semiconductor integrated circuit device according to claim 1, wherein

at least one of the cells other than the cells produced as the wiring pattern cells are made area pad cells,

the area pad cells are stored in the design library,

arrangement positions of the area pad cells are calculated based on the design library and prepared arrangement information or wiring structure information on the area pad cells, and

the area pad cells are arranged automatically.

3. The layout method for a semiconductor integrated circuit device according to claim 2, wherein the area pad cells and the wiring pattern cells have connecting pins at the boundary portions thereof.