Multi-value digital calculating circuits, including multipliers

• US 20060031278A1
• Filed: 12/20/2004
• Published: 02/09/2006
• Est. Priority Date: 08/07/2004
• Status: Active Grant

• Current Assignee: Ternarylogic LLC
• Original Assignee: Ternarylogic LLC
• Inventors: Lablans, Peter
• Granted Patent: US 7,562,106 B2
• Time in Patent Office: Days
• US Class Current: 708/670
• CPC Class Codes: G06F 7/49 Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix non-linear PCM G06F7/4824 takes precedence

Abstract

Apparatus and method for performing multi-value arithmetic operations are disclosed. Multi-value signals can be added, subtracted and multiplied using a first truth table to generate a residue and a second truth table to generate a carry. Additionally, method and apparatus to efficiently perform the function a0b1+a1b0 on multi-value signals are disclosed. Also an efficient method of processing large binary signals is disclosed.

Claims

1. A method of adding a radix-n constant to a radix-n variable, with n being greater than 2, comprising:

processing the radix-n number with a first inverter to generate a residue; and

processing the radix-n number with a second inverter to generate a carry.

2. The method of claim 1, wherein the processing with the first inverter and the processing with the second inverter are performed at the same time.

3. Apparatus for adding a radix-n constant to a radix-n variable, with n being greater than 2, comprising:

a first inverter that receives the radix-n variable and that generates a residue; and

a second inverter that receives the radix-n variable to generate a carry.

4. The apparatus of claim 3, wherein the first inverter and the second inverter are connected in parallel.

5. A method of providing a residue and a carry that solves the multi-value equation of a0b1+a1b0 with a plurality of residue tables that set forth potential solutions for the residue and a plurality of carry tables that set forth potential solutions for the carry, comprising:

accessing a table from the first plurality of residue tables based on the value of b0 and b1 to determine the residue; and

accessing a table from the plurality of carry tables based on the value of b0 and b1 to determine the carry.

6. The method as claimed in claim 5, wherein the table from the plurality of residue tables and the table from the plurality of carry tables are accessed at the same time.

7. The method of claim 5 further comprising summing the residue and the carry.

8. Apparatus for solving the multi-value arithmetic problem of a0b1+a1b0, comprising:

a first plurality of tables that provide potential residue solutions;

a second plurality of tables that provide potential carry solutions;

means for determining which table from the first plurality of tables to access based on the value of b0 and b1 to determine a residue; and

means for determining which table from the second plurality of tables to access based on the value of b0 and b1 to determine a carry.

9. The method as claimed in claim 8, wherein the table from the first plurality of tables and the table from the second plurality of tables are accessed at the same time.

10. The apparatus of claim 8 further comprising means for summing the residue and the carry.

11. A method for solving the multi-value arithmetic problem of a0b1+a1b0 wherein b0 and b1 are constants, comprising:

accessing a first logic table with a0 and a1 to determine a residue; and

accessing a second logic table with a0 and a1 to determine a carry.

12. The method of claim 11 further comprising summing the residue and the carry.

13. Apparatus for solving the multi-value arithmetic problem of a0b1+a1b0, comprising:

a first logic table;

a second logic table;

means for accessing the first logic table with a0 and a1 to determine a residue; and

means for accessing the second logic table with a0 and a1 to determine a carry.

14. The apparatus of claim 13 further comprising means for summing the residue and the carry.

15. A method of multiplying a first binary number by a second binary number, comprising:

converting the first binary number to a first multi-value number;

converting the second binary number to a second multi-value number;

multiplying the first multi-value number by the second multi-value number to determine a third multi-value number; and

converting the third multi-value number to a third binary number.

16. Apparatus for multiplying a first binary number by a second binary number, comprising:

means for converting the first binary number to a first multi-value number;

means for converting the second binary number to a second multi-value number;

means for multiplying the first multi-value number by the second multi-value number to determine a third multi-value number; and

means for converting the third multi-value number to a third binary number.

17. A method comprising filtering a digital signal y(n) in accordance with the equation

y(n)=h1*x(n)+h2*x(n−

1)+ . . . +hm*x(n−

m)

wherein x, y and hi are radix-n numbers with n greater than 2.

18. A method comprising filtering a digital signal y(n) in accordance with the equation

$y$

( n ) = ∑

i = 0 k ⁢

ai ·

x ⁡

( n - i ) + ∑

i = 1 k ⁢

bi ·

y ⁡

( n - i )

wherein x, y, ai and bi are radix-n numbers with n greater than 2.