Distributing timers across processors

• US 20060031588A1
• Filed: 06/30/2004
• Published: 02/09/2006
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sen, Sujoy, Deuskar, Prafulla, Cornett, Linden, Minturn, David B.
• Granted Patent: US 7,461,173 B2
• Time in Patent Office: Days
• US Class Current: 709/248
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/28 Timers or timing mechanisms used in protocols

Abstract

In general, in one aspect, the disclosure describes a method of maintaining network protocol timers in data structures associated with different respective processors in a multi-processor system. The timers accessed by a respective one of the processors include timers of connections mapped to the processor.

Claims

1. A method, comprising:

maintaining network protocol timers in a timer data structure associated with a processor in a multiple processor system, the timers comprising timers of connections mapped to the processor.

2. The method of claim 1, wherein the timers comprise Transmission Control Protocol (TCP) timers selected from the group of:

a time-out timer and a retransmit timer.

3. The method of claim 1, wherein the timer data structures comprises sets of timers associated with respective time buckets.

4. The method of claim 1, wherein the connections are mapped to the different, respective, processors based on a connection'"'"'s Internet Protocol (IP) source and destination addresses and Transmission Control Protocol (TCP) source and destination ports.

5. The method of claim 1, further comprising:

queuing an entry for a timer from a first one of the multiple processors into a second processor'"'"'s queue; and

dequeuing, at a second of the multiple processors, the entry from the second processor'"'"'s queue.

6. The method of claim 5, further comprising:

causing, by the first processor, a network interface controller to generate an interrupt to the second processor.

7. The method of claim 1, further comprising flagging a timer as disarmed.

8. An apparatus, comprising:

a chipset;

multiple processors coupled to the chipset; and

instructions, disposed on a computer readable medium, to cause the multiple processors to maintain different network protocol timers in multiple timer data structures associated with multiple respective processors of the multiple processor system, the timers accessed by a respective one of the processors comprising timers of connections mapped to the processor.

9. The apparatus of claim 8, wherein the timers comprise Transmission Control Protocol (TCP) timers selected from the group of:

a time-out timer and a retransmit timer.

10. The apparatus of claim 8, wherein the timer data structures comprise sets of timers associated with multiple time buckets.

11. The apparatus of claim 8, wherein the connections are mapped to the different, respective, processors based on a connection'"'"'s Internet Protocol (IP) source and destination addresses and Transmission Control Protocol (TCP) source and destination ports.

12. The apparatus of claim 8, wherein the instructions further comprise instructions to:

queue an entry for a timer from a first one of the multiple processors into a second processor'"'"'s queue; and

dequeue, at a second of the multiple processors, the entry from the second processor'"'"'s queue.

13. The apparatus of claim 8, further comprising instructions to cause, by the first processor, a network interface controller to generate an interrupt to the second processor.

14. The apparatus of claim 8, further comprising instructions to flag a timer as disarmed.

15. A computer program, disposed on a computer readable medium, comprising instructions for causing a first processor in a multi-processor system to:

dequeue a timer entry enqueued by a second processor of the multi-processor system; and

based on the dequeued timer entry, inserting a timer into a timer data structure accessed by the first processor.

16. The program of claim 15, wherein the timers comprise Transmission Control Protocol (TCP) timers selected from the group of:

a time-out time and a retransmit timer.

17. The program of claim 15, wherein the timer data structures comprises a set of time buckets and wherein different time buckets have associated lists of individual timers.

18. The program of claim 15, wherein the connections are mapped to the different, respective, processors based on a connection'"'"'s Internet Protocol (IP) source and destination addresses and Transmission Control Protocol (TCP) source and destination ports.

19. The program of claim 15, further comprising instructions for causing the processor to flag a timer as disarmed.