Ring bus structure and its use in flash memory systems

• US 20060031593A1
• Filed: 08/09/2004
• Published: 02/09/2006
• Est. Priority Date: 08/09/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Sinclair, Alan Welsh
• Granted Patent: US 8,375,146 B2
• Time in Patent Office: Days
• US Class Current: 709/251
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation

Abstract

A system and integrated circuit chips used in the system utilize a bus in the form of a ring to interconnect nodes of individual components for transfer of data and commands therebetween. An example system described is a memory having one or more re-programmable non-volatile memory cell arrays connected to each other and to a system controller by a ring bus.

Claims

1. A method of transferring data around a ring bus connecting a plurality of nodes and a controller together, comprising:

passing commands in a given direction around the ring bus from the controller to the nodes in order to establish at least one of the nodes as a source of data to be transferred and at least one other of the nodes as a destination of data to be transferred,

reading data to be transferred from memory connected to said at least one source node into temporary data storage provided at said at least one source node,

thereafter transferring the read data only in the given direction around the ring bus from the temporary data storage at said at least one source node,

thereafter writing the transferred data into temporary data storage provided at said at least one destination node, and

thereafter writing the transferred data from the temporary data storage at said at least one destination node into memory connected therewith.

2. The method of claim 1, wherein passing commands around the ring bus includes passing commands from the controller through a controller node connected into the ring bus.

3. The method of claim 2, which additionally comprises transferring data to and from a host through buffer memory included within the controller and the controller node.

4. The method of claim 1, which additionally comprises transferring data to and from a host through another node connected into the ring bus.

5. The method of claim 1, wherein passing commands includes establishing at least two of the nodes as sources of data to be transferred and at least two of the nodes as destinations of data to be transferred, wherein transferring the read data includes transferring data around the ring bus from said at least two source nodes in at least two sequential time slots and wherein writing the transferred data includes writing the data being transferred into said at least two destination nodes from different ones of said at least two sequential time slots.

6. The method of claim 5, wherein transferring the read data additionally includes adjusting the number of said at least two sequential time slots to to reduce a number of any unused time slots.

7. The method of claim 5, wherein passing commands around the ring bus does not include the use of sequential time slots.

8. The method of claim 1, wherein transferring the read data around the ring bus includes transferring the read data completely around the ring from said at least one source node and back to said at least one source node.

9. The method of claim 8, which additionally comprises verifying at said at least one source node the validity of the read data after being transferred completely around the ring.

10. The method of claim 9, wherein verifying the validity of the read data includes comparing the read data after being transferred completely around the ring with the read data placed on the ring bus at said at least one source node.

11. The method of claim 8, which additionally comprises checking the read data with an error correction scheme at a location on the ring bus.

12. The method of claim 11, wherein checking the read data with an error correction scheme occurs in the controller.

13. The method of claim 11, wherein checking the read data with an error correction scheme includes passing the data through error correction circuitry connected to the ring bus through a node in addition to said at least one source node and said at least one destination node.

14. The method of claim 1, wherein the commands passed around the ring bus to establish at least one of the nodes as a source of data to be transferred and at least one other of the nodes as a destination of data to be transferred originate only with the controller.

15. The method of claim 1, which additionally comprises, prior to transferring the read data around the ring bus, sending commands and data around the ring bus from the controller to configure the plurality of nodes.

16. The method of claim 1, wherein transferring the read data around the ring bus includes imposing a delay at individual ones of the plurality of nodes of one or more cycles of a system clock source to which the transferring read data are synchronized.

17. The method of claim 1, wherein passing commands around the ring bus includes doing so on at least a first conductor of the ring bus and transferring the read data around the ring bus includes doing so on at least a second conductor of the ring bus different from the first conductor.

18. The method of claim 1, wherein passing commands around the ring bus includes (1) establishing said at least one of the nodes as a source of data by at least one other of the plurality of nodes receiving the commands and then configuring said at least one of the nodes as a source of data, and (2) establishing said at least one of the nodes as a destination of data by at least one other of the plurality of nodes receiving the commands and then configuring said at least one of the nodes as a destination of data.

19. The method of claim 1, wherein reading data to be transferred from memory connected to said at least one source node includes reading data from at least a first unit of re-programmable non-volatile memory cells that are connected to said at least one source node.

20. The method of claim 1, wherein writing the transferred data into the memory connected with said at least one destination node includes writing the transferred data into at least a second unit of re-programmable non-volatile memory cells that are connected to said at least one destination node.

21. The method of either one of claims 19 or 20, wherein the first and second units of memory cells include respective first and second planes of less than all the memory cells on a single integrated circuit chip.

22. The method of either one of claims 19 or 20, wherein the first and second units of memory cells include an entire memory cell array on respective first and second integrated circuit chips.

23. The method of claim 2, which additionally comprises temporarily storing the read data in a buffer memory connected to another of the plurality of nodes different from the controller node, said at least one source node and said at least one destination node.

24. The method of claim 1, wherein reading data into temporary data storage includes transferring the read data into one of at least two data registers provided at said at least one source node.

25. The method of claim 1, wherein writing data into temporary data storage includes writing the transferred data into one of at least two data registers provided at said at least one destination node.

26. The method of claim 1, which additionally comprises simultaneously reading a second set of data from memory connected to one of the plurality of nodes into one portion of temporary data storage at said one of the plurality of nodes and writing a third set of data from the ring bus into another portion of temporary data storage at said one of the plurality of nodes.

27. A memory system, comprising:

at least one re-programmable non-volatile memory unit that includes a data communications node,

a host data input/output circuit having another data communications node,

a bus connecting the individual data communication nodes together in a ring, and a controller including a micro-controller operably connected with the ring bus to cause a simultaneous transfer of multiple channels of data from one or more of the data communications nodes completely around the ring bus in a single direction over a number of time-multiplexed data frames adapted to include the number of multiple channels of data being transferred.

28. The memory system of claim 27, wherein the controller is further operably connected through the ring bus to send configuration commands over the ring bus to selected ones of the communication nodes for transfer of data therethrough.

29. The memory system of claim 28, wherein the at least one memory unit additionally includes a configuration circuit and a command node connected to the ring bus and the configuration circuit for receiving and executing the configuration commands from the controller.

30. The memory system of claim 27, wherein at least the data communications node of the at least one memory unit includes at least two registers connected to simultaneously store at least two pieces of data being transferred between the memory sub-system and the ring bus.

31. The memory system of claim 27, wherein the controller includes the host data input/output circuit and the controller is connected to the ring bus through said another data communications node.

32. The memory system of claim 27, wherein the controller is connected to the ring bus through a command signal node.

33. The memory system of claim 27, wherein the at least one memory unit includes a plurality of two or more re-programmable non-volatile memory units that individually includes a data communications node.

34. The memory system of claim 33, wherein the two or more memory units include two or more memory planes on a single integrated circuit chip.

35. The memory system of claim 33, wherein the two or more memory units are formed on respective two or more separate integrated circuit chips.

36. The memory system of claim 27, which additionally comprises an error correction circuit operably connected with the ring bus to enable the multiple channels of data to pass therethrough as they are transferred around the ring bus.

37. The memory system of claim 36, wherein the controller includes the error correction circuit.

38. A flash memory system, comprising:

a plurality of flash memory data storage units that individually includes an array of flash memory cells, a data node and at least one data storage register connected between the data node and the array,

at least one command unit connected with the data storage units for communication of address and status information therebetween and connected with a command node,

a controller having an interface node,

a bus connecting together the data, command and interface nodes in a ring, and

the controller operating to transfer data among the data storage units and between the data storage units and the controller by issuing commands over the bus to the command unit, wherein said at least one register is a source or a destination of the transferred data.

39. The memory system of claim 38, wherein said at least one register includes two or more registers and the controller further operates to select through the bus one of the at least two storage registers of addressed storage units to be the source or a destination of the transferred data.

40. An integrated circuit chip, comprising:

at least two sub-arrays of re-programmable non-volatile memory cells,

at least two data storage registers, each of said at least two sub-arrays being operably connected to transfer data with at least one of the data storage registers,

at least two bus nodes, each of said at least two bus nodes being operably connected to transfer data with at least one of the data storage registers,

a first set of a plurality of external contacts providing a bus input to the integrated circuit chip,

a second set of a plurality of external contacts providing a bus output from the integrated circuit chip, and

a bus connecting said at least two bus nodes in series with the first and second sets of external contacts,

whereby the integrated circuit chip is connectable through the first and second sets of contacts in a series ring with other integrated circuit chips.

41. The integrated circuit chip of claim 40, wherein said at least two bus nodes includes a command node adapted to receive commands to configure said at least two sub-arrays and said at least two registers for transferring selected data between said at least two sub-arrays and said at least two bus nodes.

42. The integrated circuit chip of claim 40, wherein said at least two data storage registers includes at least two of said registers being operably connected to transfer data with a different one of said at least two sub-arrays.

43. An integrated circuit chip, comprising:

at least one array of re-programmable non-volatile memory cells,

at least one bus node operably connected to transfer data with said at least one array,

a first set of a plurality of external contacts providing a bus input to the integrated circuit chip,

a second set of a plurality of external contacts providing a first bus output from the integrated circuit chip for connection with input bus contacts of another integrated circuit chip containing at least one array of re-programmable non-volatile memory cells,

a third set of a plurality of external contacts providing a second bus output from the integrated circuit chip that may be enabled to establish a return bus connection, and

a bus operably connecting said at least one bus node in series with the bus input and the bus output sets of external contacts.

44. The integrated circuit chip of claim 43, wherein the third set of contacts may be enabled to provide the second bus output when the second set of contacts is not connected with input bus contacts of another integrated circuit chip containing at least one array of re-programmable non-volatile memory cells.

45. The integrated circuit chip of claim 43, which additionally comprises a circuit including temporary storage of bus data and drivers connecting the temporary storage to the third set of contacts for placing the data stored therein onto the third set of contacts, and a fourth set of a plurality of external contacts also connected on the circuit chip to the temporary storage.

46. An integrated circuit chip, comprising:

at least one array of re-programmable non-volatile memory cells,

at least one bus node operably connected to transfer data with said at least one array,

a first set of a plurality of external contacts providing a bus input to the integrated circuit chip,

a second set of a plurality of external contacts providing a bus output from the integrated circuit chip,

a bus connecting said at least one bus node in series with the first and second sets of external contacts, whereby the integrated circuit chip is connectable through the first and second sets of contacts in a series ring with other integrated circuit chips, and

wherein said at least one bus node includes temporary storage of data received on the bus and drivers to output the stored data onto the bus.

47. The integrated circuit chip of claim 46, wherein said at least one node additionally comprises a first register for storing an identification number of said at least one node and a second register for storing a channel number for data on the bus intended for said at least one node, thereby interfacing with the bus it is operated in a time multiplexed mode.