Multi-processor reconfigurable computing system

• US 20060031659A1
• Filed: 08/02/2005
• Published: 02/09/2006
• Est. Priority Date: 08/09/2004
• Status: Active Grant

• Current Assignee: Arches Computing Systems
• Original Assignee: Arches Computing Systems
• Inventors: Chow, Paul
• Granted Patent: US 7,779,177 B2
• Time in Patent Office: Days
• US Class Current: 712/11
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A reconfigurable multi-processor computing system including a plurality of configurable processing elements each having a plurality of integrated high-speed serial input/output ports. Interconnects link the plurality of processing elements, wherein at least one of the integrated high-speed serial input/output ports of each processing element is connected by at least one interconnect to at least one of the integrated high-speed serial input/output ports of each other processing element, thereby creating a full mesh network. The full mesh network is located on a processor card, multiples of which may be grouped in a shelf having a backplane card with a shelf controller card for providing cross-connects between processor cards. Multiple shelves may be interconnected to form a large computer system.

Claims

1. A configurable computing system, comprising:

a plurality of configurable processing elements each having a plurality of integrated high-speed serial input/output ports; and

interconnects between the plurality of processing elements, wherein at least one of the integrated high-speed serial input/output ports of each processing element is connected by at least one interconnect to at least one of the integrated high-speed serial input/output ports of each other processing element.

2. The computing system claimed in claim 1, wherein said interconnects and said processing elements form a full mesh network.

3. The computing system claimed in claim 1 ;

wherein said interconnects directly connect respective integrated high-speed serial input/output ports.

4. The computing system claimed in claim 3, wherein said interconnects comprise a signal path chosen from the group including an electrical path, an optical path, and an RF transmission link.

5. The computing system claimed in claim 3, wherein one integrated high-speed serial output port and one integrated high-speed serial input port on each processing element are connected to corresponding integrated high-speed serial input and output ports, respectively, on each other processing element by parallel electrical traces, and wherein the interconnected processing elements utilize differential signalling.

6. The computing system claimed in claim 1, wherein each of said plurality of configurable processing elements comprises a programmable logic device for implementing digital circuits.

7. The computing system claimed in claim 6, wherein said programmable logic devices comprise field programmable logic devices.

8. The computing system claimed in claim 7, wherein said integrated high-speed serial input/output ports of said field programmable logic devices each include an integrated serializer/deserializer transceiver and clock data recovery circuitry.

9. The computing system claimed in claim 1, wherein said processing elements and said interconnects are disposed upon a common substrate, and wherein one of said processing elements comprises a processor card control block for routing communications between said substrate and other substrates, said processor card control block including a plurality of card-level high-speed serial input/output ports for sending and receiving said communications.

10. The computing system claimed in claim 9, wherein said processor card control block includes one of said processing elements and a processor module connected by a bus.

11. The computing system claimed in claim 9, including a shelf containing a plurality of said substrates, and a backplane card for interconnecting said plurality of substrates, said backplane card including interconnectors for connecting to said card-level high-speed serial input/output ports and including a shelf control card, wherein said shelf control card provides reconfigurable cross-connects between said substrates.

12. The computing system claimed in claim 11, further including a plurality of said shelves and a system-level switch card for interconnecting said shelves.

13. The computing system claimed in claim 1, further including one or more local memory blocks connected to one of said processing elements to form a processing node.

14. A configurable processing card, comprising:

a plurality of configurable processing means for implementing digital logic circuits based upon configuration instructions, wherein said processing means includes a plurality of integrated input/output means for high-speed output serialization and input deserialization of data; and

interconnection means between the plurality of processing means for connecting at least one of the integrated input/output means on each processing means with at least one integrated input/output means of each other processing means.

15. The processing card claimed in claim 14, wherein said interconnection means and said processing means form a full mesh network.

16. The processing card claimed in claim 14, wherein one integrated input means and one integrated output means on each processing means are connected to corresponding integrated input means and integrated output means, respectively, on each other processing means by parallel electrical traces, and wherein the interconnected processing means utilize differential signalling.

17. The processing card claimed in claim 14, wherein said integrated input/output means each include an integrated serializer/deserializer transceiver means and clock data recovery means.

18. The processing card claimed in claim 15, wherein said full mesh network of processing means and said interconnection means are disposed upon a substrate, and wherein one of said processing means includes means for routing communications between said substrate and other substrates.

19. A processing shelf, comprising a plurality of said substrates as claimed in claim 18, each having one of said full mesh networks, and a backplane card for interconnecting said plurality of substrates, said backplane card including interconnection means for connecting to said means for routing communications.

20. The computer system comprising a plurality of shelves as claimed in claim 19 and a system-level switch card for interconnecting said shelves.