Method and apparatus for system monitoring with reduced function cores

• US 20060031721A1
• Filed: 08/05/2004
• Published: 02/09/2006
• Est. Priority Date: 08/05/2004
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Venton, Todd Alan, Miller, Milton Devon II, Blanchard, Anton
• Granted Patent: US 7,272,759 B2
• Time in Patent Office: Days
• US Class Current: 714/47
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3041 where the computing system component is an input/output interface interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units G06F13/00
• CPC Class Codes: G06F 11/3058 Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations thermal management in cooling arrangements of a computing system G06F1/206

Abstract

A method, apparatus, and computer instructions for monitoring a device in a data processing system. A register associated the device is accessed from a reduced function processor core through a connection between the register for the device and the reduced function processor core. The device is monitored using the value of the register.

Claims

1. A method for monitoring a device in a data processing system, the method comprising:

accessing a register associated with the device from a reduced function processor core through a connection between the register for the device and the reduced function processor core; and

monitoring the device using the value of the register.

2. The method of claim 1, wherein the connection is a bus connected to a first serial interface in the device and a second serial interface in the reduced function processor core.

3. The method of claim 1, wherein a connection to the register is accessible via an address location on a system bus.

4. The method of claim 1, wherein the device is one of a processor core, a memory controller, an I/O bridge, a fan, or a power supply.

5. The method of claim 1, wherein the register is located within the device.

7. The method of claim 5, wherein the selected processor core is one in which defects are present.

8. The method of claim 5, wherein the chip contains two processor cores.

9. The method of claim 5, wherein the value indicates a temperature of the processor core.

10. The method of claim 5, wherein the connection between the processor core and the selected processor core is a serial bus connection.

6. A method for monitoring a processor core, the method comprising:

accessing an internal register within the processor core from a selected processor core through connection between the processor core and the selected processor core; and

monitoring the processor core using the value of the internal register.

11. A data processing system for monitoring a device in the data processing system, the data processing system comprising:

accessing means for accessing a register associated with the device from a reduced function processor core through a connection between the register for the device and the reduced function processor core; and

monitoring means for monitoring the device using the value of the register.

12. The data processing system of claim 11, wherein the connection is a bus connected to a first serial interface in the device and a second serial interface in the reduced function processor core.

13. The data processing system of claim 11, wherein a connection to the register is accessible via an address location on a system bus.

14. The data processing system of claim 11, wherein the device is one of a processor core, a memory controller, an I/O bridge, a fan, or a power supply.

15. The data processing system of claim 11, wherein the register is located within the device.

16. A computer program product in a computer readable medium for monitoring a device in a data processing system, the computer program product comprising:

first instructions for accessing a register associated with the device from a reduced function processor core through a connection between the register for the device and the reduced function processor core; and

second instructions for monitoring the device using the value of the register.

17. The computer program product of claim 16, wherein the connection is a bus connected to a first serial interface in the device and a second serial interface in the reduced function processor core.

18. The computer program product of claim 16, wherein a connection to the register is accessible via an address location on a system bus.

19. The computer program product of claim 16, wherein the device is one of a processor core, a memory controller, an I/O bridge, a fan, or a power supply.

20. The computer program product of claim 16, wherein the register is located within the device.