Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
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Abstract
A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-x Gex layer is patterned and subsequently etched to form a fin on the oxide. The compressively stressed Si1-y Gey layer, having the Ge content y higher than the Ge content x in the relaxed Si1-xGex layer, is epitaxially grown on the fin. The Si1-y Gey layer covers the top and two sidewalls of the fin. The compressive stress in the Si1-y Gey layer substantially increases the hole mobility in a channel of the non-planar tri-gate p-MOS transistor structure.
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Citations
20 Claims
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1-6. -6. (canceled)
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7. A method of forming a semiconductor structure, comprising:
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forming an insulating layer;
forming a first layer of a first material on the insulating layer, the first layer having a first lattice spacing;
forming a fin having a top surface and opposing sidewalls from the first layer; and
forming a second layer of a second material on the fin, wherein the second layer of the second material covers the top surface and the opposing sidewalls of the fin and has a second lattice spacing, which is larger than the first lattice spacing. - View Dependent Claims (8, 9, 10, 11)
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12-15. -15. (canceled)
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16. A method of forming a semiconductor transistor structure, comprising:
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forming a first layer of a first material on an insulating layer on a substrate, the first layer having a first lattice spacing;
forming a first and a second fin from the first layer, the first fin being on a first portion and the second fin being on a second portion of a semiconductor transistor structure;
protecting a first portion of the semiconductor transistor structure with a first protective layer;
forming a second layer of a second material having a second lattice spacing substantially larger than the first lattice spacing on the second fin;
removing the first protective layer from the first portion of the semiconductor transistor structure and protecting the second portion of the semiconductor transistor structure with a second protective layer; and
forming a third layer of a third material having a third lattice spacing substantially smaller than the first lattice spacing on the first fin. - View Dependent Claims (17, 18, 19, 20)
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Specification