×

Three dimensional integrated circuit and method of design

  • US 20060033110A1
  • Filed: 08/16/2004
  • Published: 02/16/2006
  • Est. Priority Date: 08/16/2004
  • Status: Active Grant
First Claim
Patent Images

1. An integrated circuit (IC) comprising:

  • a stack of circuit layers including at least a first circuit layer and a second circuit layer of transistors connected together into circuit elements;

    a plurality of said circuit elements on said second circuit layer being disposed directly above a plurality of said circuit elements on first layer; and

    a plurality of interlayer connection channels, each interlayer connection channel having an end terminating on one of said circuit elements on said first layer and said second layer, ones of said circuit elements on said first layer being connected through said plurality of interlayer connection channels to corresponding ones of said circuit elements on said second layer, connection of said ones to said corresponding ones forming a three dimensional (3D) higher level circuit element within said IC.

View all claims
  • 7 Assignments
Timeline View
Assignment View
    ×
    ×