Three dimensional integrated circuit and method of design

• US 20060033110A1
• Filed: 08/16/2004
• Published: 02/16/2006
• Est. Priority Date: 08/16/2004
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Elfadel, Ibrahim M., Rahman, Arifur, Kudva, Prabhakar N., Lavin, Mark A., Ieong, Meikei, Guarini, Kathryn W., Kung, David S., Alam, Syed M.
• Granted Patent: US 7,312,487 B2
• Time in Patent Office: Days
• US Class Current: 257/74
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Claims

1. An integrated circuit (IC) comprising:

a stack of circuit layers including at least a first circuit layer and a second circuit layer of transistors connected together into circuit elements;

a plurality of said circuit elements on said second circuit layer being disposed directly above a plurality of said circuit elements on first layer; and

a plurality of interlayer connection channels, each interlayer connection channel having an end terminating on one of said circuit elements on said first layer and said second layer, ones of said circuit elements on said first layer being connected through said plurality of interlayer connection channels to corresponding ones of said circuit elements on said second layer, connection of said ones to said corresponding ones forming a three dimensional (3D) higher level circuit element within said IC.

2. An IC as in claim 1, wherein at least one of said stack of circuit layers is a wiring layer disposed between a pair of adjacent said circuit layers, another end of said ones of said plurality of interlayer connection channels being connected to wiring on said wiring layer.

3. An IC as in claim 1, wherein at least one of circuit elements on said first circuit layer shares a interlayer connection channel with a corresponding circuit element on said second circuit layer.

4. An IC as in claim 1, wherein said first circuit layer is a silicon on insulator (SOI) CMOS circuit layer.

5. An IC as in claim 4, wherein said second circuit layer includes an array of active circuit elements.

6. An IC as in claim 5, wherein said circuit elements on said SOI CMOS circuit layer comprise combinational logic and said array of active circuit elements is a CMOS driver grid, selected drivers of said driver grid being power up buffers for corresponding combinational logic gates on said SOI CMOS circuit layer.

7. An IC as in claim 4, wherein said second layer comprises a clock distribution for said SOI CMOS circuit layer.

8. An IC as in claim 7, wherein said clock distribution comprises a plurality of CMOS clock drivers.

9. An IC as in claim 4, wherein a majority of IC chip said circuit elements are located on said SOI CMOS circuit layer.

10. An IC as in claim 4, wherein said second layer is a SOI CMOS circuit layer.

11. An integrated circuit (IC) chip comprising:

a substrate layer;

a first insulating layer on said substrate layer;

a first semiconductor layer on said first insulating layer, transistors being formed from said first semiconductor layer;

a second insulating layer attached to said first semiconductor layer;

a second semiconductor layer on said second insulating layer, transistors being formed from said second semiconductor layer, said transistors at each of said first semiconductor layer and said second semiconductor layer being connected together into circuit elements in a circuit layer; and

a plurality of interlayer connection channels, each interlayer connection channel having an end terminating on and extending from one of said circuit elements on said first semiconductor layer and said second semiconductor second layer, ones of said circuit elements on said first semiconductor layer being connected through said plurality of interlayer connection channels to corresponding ones of said circuit elements on said second semiconductor layer, connection of said ones to said corresponding ones forming a three dimensional (3D) higher level circuit element within said IC.

12. An IC chip as in claim 11, wherein said first semiconductor layer is a silicon layer and said substrate layer, said first insulating layer and said silicon layer are layers in a silicon on insulator (SOI) CMOS circuit layer.

13. An IC chip as in claim 12, wherein said SOI CMOS circuit layer further comprises a wiring layer above said silicon layer, said transistors being connected together by wiring in said wiring layer and said IC further comprises a polymeric adhesive layer bonding said second insulating layer and said SOI CMOS circuit layer, said polymeric adhesive layer attaching said second semiconductor layer to said SOI CMOS circuit layer, said plurality of interlayer connection channels extending linearly between said ones and said corresponding ones.

14. An IC chip as in claim 12, further comprising a wiring layer disposed between said SOI CMOS circuit layer and said second semiconductor layer, another end of ones of said plurality of interlayer connections being connected to wires on said wiring layer.

15. An IC chip as in claim 11, wherein said second semiconductor layer includes an array of circuit elements.

16. An IC chip as in claim 15, wherein said circuit elements on said SOI CMOS circuit layer include combinational logic and said array of circuit elements is a CMOS driver grid, selected drivers of said CMOS driver grid being power up buffers for corresponding combinational logic gates on said SOI CMOS circuit layer.

17. An IC chip as in claim 14, wherein said second semiconductor layer includes a clock distribution for said SOI CMOS circuit layer.

18. An IC chip as in claim 17, wherein said clock distribution includes a plurality of CMOS clock drivers.

19. An IC chip as in claim 14, wherein a majority of IC chip elements are located on said SOI CMOS circuit layer.

20. An IC chip as in claim 14, wherein said second insulator layer and said second semiconductor layer are layers in a second SOI CMOS circuit layer.

21. A method of fabricating an integrated circuit (IC) chip, said method comprising the steps of:

a) providing an IC design;

b) placing and wiring said IC design, circuit elements being placed on at least two circuit layers, selected said circuit elements of a first circuit layer of said at least two circuit layers being wired to corresponding circuit elements on a second circuit layer of said at least two;

c) fabricating said at least two circuit layers;

d) attaching said second circuit layer to said second circuit layer; and

e) forming connection channels extending from circuit elements in said first circuit layer and in said second circuit layer, a three dimensional (3D) IC being formed by said circuit elements in said first circuit layer being connected to said circuit elements in said second circuit layer.

22. A method as in claim 21, wherein the step (b) of placing and wiring comprises the steps of:

i) placing a majority of circuit elements in said first circuit layer; and

ii) placing remaining circuit elements on said second circuit layer.

23. A method as in claim 22, wherein the step (i) of placing a majority of elements comprises the steps of:

A) initially placing and wiring logic in said IC design on a single layer;

B) conducting performance analysis on the placed and wired said logic; and

C) placing and wiring said buffers on said second circuit layer.

24. A method as in claim 23, wherein the step (C) of placing and wiring includes placing and wiring selected said circuit elements originally placed on said single layer.

25. A method as in claim 22, wherein said second circuit layer is an array of circuit elements and the step (ii) of placing said remaining circuit elements comprises selecting ones from said array.

26. A method as in claim 21, wherein the step (c) of fabricating said at least two layers comprises fabricating a first of said at least two on a first silicon on insulator (SOI) wafer and a second of said at least two on a second SOI wafer.

27. A method as in claim 26, wherein the step (d) of attaching comprises the steps of:

i) attaching a glass handle wafer to said second SOI wafer;

ii) removing a substrate layer from said second SOI wafer; and

iii) attaching said second SOI wafer to said first SOI wafer, said first SOI wafer providing a substrate for said second SOI wafer.

28. A method as in claim 27, further comprising the step of:

e) dicing stacked second SOI wafer and said first SOI wafer into individual three dimensional (3D) laminated chips.

29. A method of placing and wiring a circuit design, said method comprising the steps of:

a) receiving an integrated circuit design;

b) initially placing and wiring a majority of design circuit elements in said first circuit layer;

c) conducting performance analysis on the placed and wired said first circuit layer;

d) selectively removing circuit elements placed on said first circuit layer;

e) placing remaining circuit elements and removed said circuit elements on said second circuit layer; and

f) wiring said second layer, elements on said second circuit layer being connected to corresponding elements on said first circuit layer.

30. A method as in claim 29, wherein said circuit elements remaining after the step (b) of initially placing and wiring are buffers for combinational logic on said first circuit layer.

31. A method as in claim 29, wherein the step (e) of placing said remaining circuit elements comprises selecting circuit elements from an array of circuit elements.

32. A method as in claim 33, wherein said array of circuit elements is an array of drivers.