Method for fabrication of semiconductor device

• US 20060033124A1
• Filed: 10/03/2005
• Published: 02/16/2006
• Est. Priority Date: 12/18/2002
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: eASIC Corporation (Intel Corporation)
• Inventors: Or-Bach, Zvi, Cooke, Laurance
• Application Number:
  US11/240,380
• Publication Number:
  US 20060033124A1
• Time in Patent Office: Days
• US Class Current: 257/202
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.

Claims

1-62. -62. (canceled)

63. A device comprising:

a borderless logic array;

area I/Os;

a redistribution layer to redistribute one or more of said area I/Os; and

at least one pad to connect said device to at least one other device, wherein at least one said pad overlays at least a portion of the logic array or a portion of the area I/Os.

64. The device according to claim 63, further comprising:

a borderless memory array.

65. The device according to claim 63, wherein said logic array comprises:

a module array.

66. A device comprising:

a borderless logic array, including one or more logic array interconnections, wherein said one or more logic array interconnections comprise metal layers and via layers, and wherein at least one of said metal layers comprises at least one substantially repeating pattern for a portion used for said logic array interconnections;

area I/Os; and

a redistribution layer.

67. The device according to claim 66, wherein at least two of said metal layers comprise substantially repeating patterns for portions used for said logic array interconnections.

68. A device according to claim 66, wherein at least three of said metal layers comprise substantially repeating patterns for portions used for said logic array interconnections.

69. A device comprising:

a borderless logic array;

area I/Os positioned in a non-surrounding fashion with respect to said borderless logic array; and

a redistribution layer to redistribute at least some of said area I/Os.

70. A device comprising:

a borderless logic array, the borderless logic array comprising a repeating module;

area I/Os positioned in a non-surrounding fashion with respect to at least one of said repeating modules; and

a redistribution layer to redistribute at least some of said area I/Os.

71. A device comprising:

a borderless logic array, comprising a repeating core;

area I/Os, at least one of said area I/Os being a configurable I/O; and

a redistribution layer for redistributing at least some of said area I/Os.

72. A device comprising:

a borderless logic array;

area I/Os, wherein at least one of said area I/Os comprises a via-configurable I/O.

73. The device as in claim 72, further comprising:

a redistribution layer for redistributing at least some of said area I/Os.

74. A device comprising:

a logic array; and

via-configurable I/Os, wherein at least one of said via-configurable I/Os contains a structure to enable the via-configurable I/O to be configured in the following forms;

as a single-ended input;

as a single-ended output;

as a portion of a differential input pair; and

as a portion of a differential output pair.