Error recovery in asynchronous combinational logic circuits
First Claim
1. A system for providing error recovery to an asynchronous logic circuit, comprising in combination:
- a plurality of asynchronous register voters for receiving outputs from the asynchronous logic circuit, wherein the plurality of asynchronous register voters provide an output indicating a non-data state value if an inconsistent result is detected; and
a plurality of voter gates for receiving an common input from each of the plurality of asynchronous register voters, wherein the plurality of voter gates compares the common inputs from each of the plurality of asynchronous register voters, wherein the plurality of voter gate provides an output having a same logic level as a majority of the common inputs from the plurality of asynchronous register voters, wherein the output from the plurality of voter gates is representative of the outputs from the asynchronous logic circuit.
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Abstract
A system and method for providing error recovery to an asynchronous logic circuit is presented. The asynchronous logic circuit with error recovery may use temporal redundancy to compare the results of an asynchronous computation and initiate error recovery if necessary. Outputs of the asynchronous logic circuit are compared using a plurality of asynchronous register voters. If an asynchronous register voter detects an inconsistent result, the asynchronous register voter clears itself. A majority of common data outputs from the plurality of asynchronous register voters is provided as an output that is representative of the output of the asynchronous logic circuit.
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Citations
41 Claims
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1. A system for providing error recovery to an asynchronous logic circuit, comprising in combination:
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a plurality of asynchronous register voters for receiving outputs from the asynchronous logic circuit, wherein the plurality of asynchronous register voters provide an output indicating a non-data state value if an inconsistent result is detected; and
a plurality of voter gates for receiving an common input from each of the plurality of asynchronous register voters, wherein the plurality of voter gates compares the common inputs from each of the plurality of asynchronous register voters, wherein the plurality of voter gate provides an output having a same logic level as a majority of the common inputs from the plurality of asynchronous register voters, wherein the output from the plurality of voter gates is representative of the outputs from the asynchronous logic circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A system for providing error recovery to an asynchronous logic circuit, comprising in combination:
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a first asynchronous register for providing inputs to the asynchronous logic circuit;
a plurality of asynchronous register voters for receiving outputs from the asynchronous logic circuit, wherein the plurality of asynchronous register voters provide an output indicating a non-data state value if an inconsistent result is detected;
a plurality of voter gates for receiving a common input from each of the plurality of asynchronous register voters, wherein the plurality of voter gates compares the common inputs from each of the plurality of asynchronous register voters, wherein the plurality of voter gates provide an output having a same logic level as a majority of the common inputs from the plurality of asynchronous register voters; and
a second asynchronous register for receiving the outputs from the plurality of voter gates, wherein the second asynchronous register provides an output representative of the output of the asynchronous logic circuit, wherein inconsistent results are detected and corrected prior to the second asynchronous register providing the output. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A system for providing error recovery to an asynchronous logic circuit, comprising in combination:
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a first asynchronous register for providing inputs to the asynchronous logic circuit;
a first asynchronous register voter, a second asynchronous register voter, and a third asynchronous register voter, wherein the first, second, and third asynchronous register voters are connected to outputs of the asynchronous logic circuit, wherein the first, second, and third asynchronous register voters provide an output indicating a non-data state value if an inconsistent result is detected;
a counter that selects one of the first, second, and third asynchronous register voters to latch the outputs of the asynchronous logic circuit;
a data ready gate connected to the outputs of the asynchronous logic circuit, wherein the data ready gate is operable to detect a DATA wave front on the outputs of the asynchronous logic circuit;
wherein the data ready gate causes a NULL wave front to propagate through the asynchronous logic circuit, and wherein the data ready gate signals to the counter to count;
a voter gate for each common input from the first, second, and third asynchronous register voters, wherein the voter gate compares the common input from the first, second, and third asynchronous register voters, wherein the voter gate provides an output having a same logic level as a majority of the common inputs from the first, second, and third asynchronous register voters; and
a second asynchronous register for receiving the output from the voter gate, wherein the second asynchronous register provides an output representative of the output of the asynchronous logic circuit, wherein inconsistent results are detected and corrected prior to the second asynchronous register providing the output. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26)
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27. A method for providing error recovery to an asynchronous logic circuit, comprising in combination:
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detecting an inconsistent result;
clearing an asynchronous register voter upon detection of the inconsistent result;
comparing common data outputs of a plurality of asynchronous register voters; and
providing an output of the asynchronous logic circuit based on a majority of the common data outputs from the plurality of asynchronous register voters. - View Dependent Claims (28, 29, 30, 31, 32)
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33. A method for providing error recovery to an asynchronous logic circuit, comprising in combination:
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detecting a first DATA wave front at an output of an asynchronous logic circuit;
propagating a NULL wave front through the asynchronous logic circuit;
resetting the asynchronous logic circuit using the data preserved in an asynchronous register;
detecting a second DATA wave front at the output of the asynchronous logic circuit;
comparing the first and second DATA wave front;
if the first and second DATA wave fronts are not the same, propagating a NULL wave front through the asynchronous logic circuit;
resetting the asynchronous logic circuit using the data preserved in the asynchronous register;
detecting a third DATA wave front at the output of the asynchronous logic circuit; and
selecting an output based on a majority of the first, second, and third DATA wave fronts. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41)
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Specification