Integrated header switch with low-leakage PMOS and high-leakage NMOS transistors
First Claim
1. A combination header switch for use in providing power to circuitry in an integrated circuit, the combination header switch comprising:
- a PMOS (P-type Metal Oxide Semiconductor) transistor having a gate terminal coupled to a first control signal line, the PMOS transistor also having a first source/drain terminal and a second source/drain terminal;
an NMOS (N-type Metal Oxide Semiconductor) transistor having a gate terminal coupled to a second control signal line, the NMOS transistor also having a first source/drain terminal and a second source/drain terminal; and
wherein the first source/drain terminal of the PMOS transistor and the first source/drain terminal of the NMOS transistor are coupled to a voltage supply and wherein the second source/drain terminal of the PMOS transistor and the second source/drain terminal of the NMOS transistor are coupled to an output of the combination header switch.
1 Assignment
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Accused Products
Abstract
System and method for providing power with a large on-current and small off-current to circuitry in an integrated circuit. A preferred embodiment comprises a switch for providing power to circuits in an integrated circuit made from a PMOS transistor and an NMOS transistor coupled in parallel. Each transistor'"'"'s gate terminal is coupled to a separate control signal line. The PMOS transistor provides current to the circuits at high voltage supply levels while the NMOS transistor provides current to the circuits at low voltage supply levels, wherein the size of the PMOS and NMOS transistor can be changed during design to meet power requirements. Depending upon power requirements, multiple PMOS and NMOS transistors may be used. The combination of PMOS and NMOS transistors permit the use of limited fabrication processes wherein transistor widths can be limited.
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Citations
22 Claims
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1. A combination header switch for use in providing power to circuitry in an integrated circuit, the combination header switch comprising:
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a PMOS (P-type Metal Oxide Semiconductor) transistor having a gate terminal coupled to a first control signal line, the PMOS transistor also having a first source/drain terminal and a second source/drain terminal;
an NMOS (N-type Metal Oxide Semiconductor) transistor having a gate terminal coupled to a second control signal line, the NMOS transistor also having a first source/drain terminal and a second source/drain terminal; and
wherein the first source/drain terminal of the PMOS transistor and the first source/drain terminal of the NMOS transistor are coupled to a voltage supply and wherein the second source/drain terminal of the PMOS transistor and the second source/drain terminal of the NMOS transistor are coupled to an output of the combination header switch. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An integrated circuit comprising:
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a logic circuit; and
a combination header switch coupled between a voltage supply and the logic circuit, the combination header switch configured to provide current to the logic circuit as a function of the level of the voltage supply, and wherein the combination header switch comprises;
a plurality of NMOS transistors coupled in parallel, each NMOS transistor having a first source/drain terminal coupled to the voltage supply, a second source/drain terminal coupled to the logic circuit, and a gate terminal coupled to a first control signal line; and
a plurality of PMOS transistors coupled in parallel, each PMOS transistor having a first source/drain terminal coupled to the voltage supply, a second source/drain terminal coupled to the logic circuit, and a gate terminal coupled to the first control signal line. - View Dependent Claims (14)
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15. A method for designing an integrated circuit, the method comprising:
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specifying frequency targets for operation of logic gates within the integrated circuit;
determining currents to flow to the logic gates, the determining being based on the frequency targets; and
sizing a combination header switch that will be coupled between the logic gates and a voltage supply so that the combination header switch can provide the determined currents. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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Specification