Integrated header switch with low-leakage PMOS and high-leakage NMOS transistors

• US 20060033525A1
• Filed: 08/11/2004
• Published: 02/16/2006
• Est. Priority Date: 08/11/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Scott, David B., Mair, Hugh T., Lagerquist, Rolf
• Granted Patent: US 7,164,291 B2
• Time in Patent Office: Days
• US Class Current: 326/33
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption

Abstract

System and method for providing power with a large on-current and small off-current to circuitry in an integrated circuit. A preferred embodiment comprises a switch for providing power to circuits in an integrated circuit made from a PMOS transistor and an NMOS transistor coupled in parallel. Each transistor'"'"'s gate terminal is coupled to a separate control signal line. The PMOS transistor provides current to the circuits at high voltage supply levels while the NMOS transistor provides current to the circuits at low voltage supply levels, wherein the size of the PMOS and NMOS transistor can be changed during design to meet power requirements. Depending upon power requirements, multiple PMOS and NMOS transistors may be used. The combination of PMOS and NMOS transistors permit the use of limited fabrication processes wherein transistor widths can be limited.

Claims

1. A combination header switch for use in providing power to circuitry in an integrated circuit, the combination header switch comprising:

a PMOS (P-type Metal Oxide Semiconductor) transistor having a gate terminal coupled to a first control signal line, the PMOS transistor also having a first source/drain terminal and a second source/drain terminal;

an NMOS (N-type Metal Oxide Semiconductor) transistor having a gate terminal coupled to a second control signal line, the NMOS transistor also having a first source/drain terminal and a second source/drain terminal; and

wherein the first source/drain terminal of the PMOS transistor and the first source/drain terminal of the NMOS transistor are coupled to a voltage supply and wherein the second source/drain terminal of the PMOS transistor and the second source/drain terminal of the NMOS transistor are coupled to an output of the combination header switch.

2. The combination header switch of claim 1, wherein a threshold voltage of the PMOS transistor is larger than a threshold voltage of the NMOS transistor and a width of the PMOS transistor is greater than a width of the NMOS transistor.

3. The combination header switch of claim 2, wherein the PMOS transistor comprises a plurality of PMOS transistors and the NMOS transistor comprises a plurality of NMOS transistors, and wherein a total width of the plurality of PMOS transistors is greater than a total width of the plurality of NMOS transistors.

4. The combination header switch of claim 3, wherein the total width of the plurality of PMOS transistors is greater than 10 times the total width of the plurality of NMOS transistors.

5. The combination header switch of claim 1, wherein the first and the second control signal lines carry control signals based on a single control signal.

6. The combination header switch of claim 1, wherein the PMOS transistor comprises a plurality of PMOS transistors coupled in parallel, each PMOS transistor having a first source/drain terminal coupled to the voltage supply, a second source/drain terminal coupled to the output, and a gate terminal coupled to the first control signal line, wherein the NMOS transistor comprises a plurality of NMOS transistors coupled in parallel, each NMOS transistor having a first source/drain terminal coupled to the voltage supply, a second source/drain terminal coupled to the output, and a gate terminal coupled to the first control signal line, wherein a size of the NMOS transistor is used to determine the number of NMOS transistors in the plurality of NMOS transistors and wherein a size of the PMOS transistor is used to determine the number of PMOS transistors in the plurality of PMOS transistors, wherein the size of the PMOS transistor and the size of the NMOS transistor is selected to provide a required current level to the circuitry as a function of voltage supply level.

7. The combination header switch of claim 1, wherein the PMOS transistor comprises a plurality of PMOS transistors coupled in parallel, each PMOS transistor having a first source/drain terminal coupled to the voltage supply, a second source/drain terminal coupled to the output, and a gate terminal coupled to the first control signal line.

8. The combination header switch of claim 1, wherein the NMOS transistor comprises a plurality of NMOS transistors coupled in parallel, each NMOS transistor having a first source/drain terminal coupled to the voltage supply, a second source/drain terminal coupled to the output, and a gate terminal coupled to the first control signal line.

9. The combination header switch of claim 1, wherein the PMOS transistor is an I/O (input/output) transistor.

10. The combination header switch of claim 1, wherein the NMOS transistor is a core transistor.

11. The combination header switch of claim 1, wherein the first source/drain terminal of the PMOS transistor is a source terminal, wherein the second source/drain terminal of the PMOS transistor is a drain terminal, wherein the first source/drain terminal of the NMOS transistor is a drain terminal, and wherein the second source/drain terminal of the NMOS transistor is the source terminal.

12. The combination header switch of claim 1, wherein the size of the PMOS transistor and the size of the NMOS transistor are selected to provide required current levels to the circuitry as a function of voltage supply level.

13. An integrated circuit comprising:

a logic circuit; and

a combination header switch coupled between a voltage supply and the logic circuit, the combination header switch configured to provide current to the logic circuit as a function of the level of the voltage supply, and wherein the combination header switch comprises;

a plurality of NMOS transistors coupled in parallel, each NMOS transistor having a first source/drain terminal coupled to the voltage supply, a second source/drain terminal coupled to the logic circuit, and a gate terminal coupled to a first control signal line; and

a plurality of PMOS transistors coupled in parallel, each PMOS transistor having a first source/drain terminal coupled to the voltage supply, a second source/drain terminal coupled to the logic circuit, and a gate terminal coupled to the first control signal line.

14. The integrated circuit of claim 13, the number of NMOS transistors in the plurality of NMOS transistors is determined by a size of a designed NMOS transistor and wherein the number of PMOS transistors in the plurality of PMOS transistors is determined by a size of a designed PMOS transistor, wherein the size of the designed PMOS transistor and the size of the designed NMOS transistor is selected to provide a required current level to the circuitry as a function of voltage supply level.

15. A method for designing an integrated circuit, the method comprising:

specifying frequency targets for operation of logic gates within the integrated circuit;

determining currents to flow to the logic gates, the determining being based on the frequency targets; and

sizing a combination header switch that will be coupled between the logic gates and a voltage supply so that the combination header switch can provide the determined currents.

16. The method of claim 15, wherein the combination header switch comprises a plurality of PMOS transistors coupled in parallel with a plurality of NMOS transistors, and wherein sizing the combination header switch determines the number of transistors in the plurality of PMOS transistors and the number of transistors in the plurality of NMOS transistors.

17. The method of claim 16, wherein the frequency targets are specified for a range of voltage supply levels.

18. The method of claim 17, wherein there are a plurality of frequency targets, and wherein the currents are determined by multiplying each frequency target with an associated voltage supply level.

19. The method of claim 16, wherein the frequency targets are specified for a range of voltage supply levels, and wherein the sizing comprises:

selecting the number of PMOS transistors to provide current at high voltage supply levels; and

selecting the number of NMOS transistors to provide current at low voltage supply levels.

20. The method of claim 16 further comprising after the sizing, verifying that the combination header switch can provide the determined currents.

21. The method of claim 20, wherein the sizing and verifying is repeated until the combination header switch can provide the determined currents.

22. The method of claim 15, wherein the frequency targets are specified for a range of voltage supply levels, and wherein the sizing comprises:

determining a width and a length of the PMOS transistor to provide current at high voltage supply levels; and

determining a width and a length of the NMOS transistor to provide current at low voltage supply levels.