Semiconductor device and manufacturing method of the same

• US 20060033526A1
• Filed: 08/15/2005
• Published: 02/16/2006
• Est. Priority Date: 08/16/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Yamamoto, Kenji
• Granted Patent: US 7,212,031 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

A semiconductor device has a plurality of universal logic cells, a power supply line, a ground line, a first interconnection and a second interconnection. Each universal logic cell includes first to seventh nodes formed in a top layer of common interconnection layers which are allocated to the universal logic cells. The first interconnection connects the third node, the fourth node and the fifth node, and the second interconnection connects the power supply line and the first node. Or, the first interconnection connects the second node, the sixth node and the seventh node, and the second interconnection connects the ground line and the first node. The first and second interconnections are formed in a customize interconnection layer provided on the common interconnection layers.

Claims

1. A semiconductor device comprising:

a plurality of universal logic cells;

a power supply line;

a ground line;

a first interconnection; and

a second interconnection,

wherein each of said plurality of universal logic cells includes;

an inverter whose input is connected to a first node;

a first P-channel transistor whose gate, source and drain are connected to a second node, said power supply line and a fourth node, respectively;

a first N-channel transistor whose gate, source and drain are connected to said second node, said ground line and a fifth node, respectively;

a first transfer gate including a P-channel transistor whose gate is connected to said first node, wherein an input and an output of said first transfer gate are connected to said fourth node and an output terminal, respectively;

a second transfer gate including an N-channel transistor whose gate is connected to an output of said inverter, wherein an input and an output of said second transfer gate are connected to said fifth node and said output terminal, respectively;

a second P-channel transistor whose gate, source and drain are connected to a third node, said power supply line and a sixth node, respectively;

a second N-channel transistor whose gate, source and drain are connected to said third node, said ground line and a seventh node, respectively;

a third transfer gate including a P-channel transistor whose gate is connected to an output of said inverter, wherein an input and an output of said third transfer gate are connected to said sixth node and said output terminal, respectively; and

a fourth transfer gate including an N-channel transistor whose gate is connected to said first node, wherein an input and an output of said fourth transfer gate are connected to said seventh node and said output terminal, respectively,

wherein said first interconnection connects said third node, said fourth node and said fifth node of a first universal logic cell of said plurality of universal logic cells, and

said second interconnection connects said power supply line and said first node of said first universal logic cell.

2. The semiconductor device according to claim 1, further comprising:

a third interconnection;

a fourth interconnection; and

an inter-cell interconnection,

wherein said third interconnection connects said third node, said fourth node and said fifth node of a second universal logic cell of said plurality of universal logic cells,

said fourth interconnection connects said power supply line and said first node of said second universal logic cell, and

said inter-cell interconnection connects said output terminal of said first universal logic cell and said second node of said second universal logic cell.

3. The semiconductor device according to claim 1, wherein said plurality of universal logic cells are arranged in a matrix.

4. The semiconductor device according to claim 1, wherein at least a portion of an interconnection of each of said first node, said third node, said fourth node and said fifth node is formed in a top layer of common interconnection layers which are allocated to said each universal logic cell, while said first interconnection and said second interconnection are formed in a customize interconnection layer provided on said common interconnection layers.

5. The semiconductor device according to claim 2, wherein at least a portion of an interconnection of each of said first node, said second node, said third node, said fourth node, said fifth node and said output terminal is formed in a top layer of common interconnection layers which are allocated to said each universal logic cell, while said first interconnection, said second interconnection, said third interconnection, said fourth interconnection and said inter-cell interconnection are formed in a customize interconnection layer provided on said common interconnection layers.

6. A semiconductor device comprising:

a plurality of universal logic cells;

a power supply line;

a ground line;

a first interconnection; and

a second interconnection,

wherein each of said plurality of universal logic cells includes;

an inverter whose input is connected to a first node;

a first P-channel transistor whose gate, source and drain are connected to a second node, said power supply line and a fourth node, respectively;

a first N-channel transistor whose gate, source and drain are connected to said second node, said ground line and a fifth node, respectively;

a first transfer gate including a P-channel transistor whose gate is connected to said first node, wherein an input and an output of said first transfer gate are connected to said fourth node and an output terminal, respectively;

a second transfer gate including an N-channel transistor whose gate is connected to an output of said inverter, wherein an input and an output of said second transfer gate are connected to said fifth node and said output terminal, respectively;

a second P-channel transistor whose gate, source and drain are connected to a third node, said power supply line and a sixth node, respectively;

a second N-channel transistor whose gate, source and drain are connected to said third node, said ground line and a seventh node, respectively;

a third transfer gate including a P-channel transistor whose gate is connected to an output of said inverter, wherein an input and an output of said third transfer gate are connected to said sixth node and said output terminal, respectively; and

a fourth transfer gate including an N-channel transistor whose gate is connected to said first node, wherein an input and an output of said fourth transfer gate are connected to said seventh node and said output terminal, respectively,

wherein said first interconnection connects said second node, said sixth node and said seventh node of a first universal logic cell of said plurality of universal logic cells, and

said second interconnection connects said ground line and said first node of said first universal logic cell.

7. The semiconductor device according to claim 6, further comprising:

a third interconnection;

a fourth interconnection; and

an inter-cell interconnection,

wherein said third interconnection connects said second node, said sixth node and said seventh node of a second universal logic cell of said plurality of universal logic cells,

said fourth interconnection connects said ground line and said first node of said second universal logic cell, and

said inter-cell interconnection connects said output terminal of said first universal logic cell and said third node of said second universal logic cell.

8. The semiconductor device according to claim 6, wherein said plurality of universal logic cells are arranged in a matrix.

9. The semiconductor device according to claim 6, wherein at least a portion of an interconnection of each of said first node, said second node, said sixth node and said seventh node is formed in a top layer of common interconnection layers which are allocated to said each universal logic cell, while said first interconnection and said second interconnection are formed in a customize interconnection layer provided on said common interconnection layers.

10. The semiconductor device according to claim 7, wherein at least a portion of an interconnection of each of said first node, said second node, said third node, said sixth node, said seventh node and said output terminal is formed in a top layer of common interconnection layers which are allocated to said each universal logic cell, while said first interconnection, said second interconnection, said third interconnection, said fourth interconnection and said inter-cell interconnection are formed in a customize interconnection layer provided on said common interconnection layers.

11. A semiconductor device comprising:

a plurality of universal logic cells;

a power supply line; and

a ground line,

wherein each of said plurality of universal logic cells includes;

an inverter whose input is connected to a first node;

a first P-channel transistor whose gate, source and drain are connected to a second node, said power supply line and a fourth node, respectively;

a first N-channel transistor whose gate, source and drain are connected to said second node, said ground line and a fifth node, respectively;

a first transfer gate including a P-channel transistor whose gate is connected to said first node, wherein an input and an output of said first transfer gate are connected to said fourth node and an output terminal, respectively;

a second transfer gate including an N-channel transistor whose gate is connected to an output of said inverter, wherein an input and an output of said second transfer gate are connected to said fifth node and said output terminal, respectively;

a second P-channel transistor whose gate, source and drain are connected to a third node, said power supply line and a sixth node, respectively;

a second N-channel transistor whose gate, source and drain are connected to said third node, said ground line and a seventh node, respectively;

a third transfer gate including a P-channel transistor whose gate is connected to an output of said inverter, wherein an input and an output of said third transfer gate are connected to said sixth node and said output terminal, respectively; and

a fourth transfer gate including an N-channel transistor whose gate is connected to said first node, wherein an input and an output of said fourth transfer gate are connected to said seventh node and said output terminal, respectively,

wherein at least a portion of an interconnection of each of said first node, said second node, said third node, said fourth node, said fifth node, said sixth node, said seventh node and said output terminal is formed in a top layer of common interconnection layers which are allocated to said each universal logic cell.

12. The semiconductor device according to claim 11, further comprising a via formed on said top layer.

13. The semiconductor device according to claim 11, further comprising:

a first interconnection; and

a second interconnection,

wherein said first interconnection connects said third node, said fourth node and said fifth node of a first universal logic cell of said plurality of universal logic cells, and

said second interconnection connects said power supply line and said first node of said first universal logic cell.

14. The semiconductor device according to claim 13, wherein said first interconnection and said second interconnection are formed in a customize interconnection layer provided on said common interconnection layers.

15. The semiconductor device according to claim 13, further comprising:

a third interconnection;

a fourth interconnection; and

an inter-cell interconnection,

wherein said third interconnection connects said third node, said fourth node and said fifth node of a second universal logic cell of said plurality of universal logic cells,

said fourth interconnection connects said power supply line and said first node of said second universal logic cell, and

said inter-cell interconnection connects said output terminal of said first universal logic cell and said second node of said second universal logic cell.

16. The semiconductor device according to claim 15, wherein said first interconnection, said second interconnection, said third interconnection, said fourth interconnection and said inter-cell interconnection are formed in a customize interconnection layer provided on said common interconnection layers.

17. The semiconductor device according to claim 11, further comprising:

a first interconnection; and

a second interconnection,

wherein said first interconnection connects said second node, said sixth node and said seventh node of a first universal logic cell of said plurality of universal logic cells, and

said second interconnection connects said ground line and said first node of said first universal logic cell.

18. The semiconductor device according to claim 17, wherein said first interconnection and said second interconnection are formed in a customize interconnection layer provided on said common interconnection layers.

19. The semiconductor device according to claim 17, further comprising:

a third interconnection;

a fourth interconnection; and

an inter-cell interconnection,

wherein said third interconnection connects said second node, said sixth node and said seventh node of a second universal logic cell of said plurality of universal logic cells,

said fourth interconnection connects said ground line and said first node of said second universal logic cell, and

said inter-cell interconnection connects said output terminal of said first universal logic cell and said third node of said second universal logic cell.

20. The semiconductor device according to claim 19, wherein said first interconnection, said second interconnection, said third interconnection, said fourth interconnection and said inter-cell interconnection are formed in a customize interconnection layer provided on said common interconnection layers.