Thin film transistor array panel

• US 20060033871A1
• Filed: 10/18/2005
• Published: 02/16/2006
• Est. Priority Date: 12/03/2004
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Chang-Hun, Kim, Hyun-Wuk, Lyu, Jae-Jin, Um, Yoon-Sung
• Application Number:
  US11/254,134
• Publication Number:
  US 20060033871A1
• Time in Patent Office: Days
• US Class Current: 349/139
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line

Abstract

A thin film transistor array panel according to one embodiment of the invention comprises: first, second, and third pixel electrodes arranged sequentially, the second pixel electrode including first and second sub-pixel electrodes, the second pixel electrode occupying an area comprising a first area and a second area that is disposed closer to the third pixel electrode than the first area; first, second, and third thin film transistors connected to the first, the second, and the third pixel electrodes, respectively; first, second, and third gate lines connected to the first, the second, and the third thin film transistors, respectively; and a data line connected to the first, the second, and the third thin film transistors, wherein the second sub-pixel electrode is capacitively coupled to the third pixel electrode, and the second sub-pixel electrode is present in both the first and the second areas.

Claims

1. A thin film transistor array panel comprising:

first, second, and third pixel electrodes arranged sequentially, the second pixel electrode including first and second sub-pixel electrodes, the second pixel electrode occupying an area comprising a first area and a second area that is disposed closer to the third pixel electrode than the first area;

first, second, and third thin film transistors connected to the first, the second, and the third pixel electrodes, respectively;

first, second, and third gate lines connected to the first, the second, and the third thin film transistors, respectively; and

a data line connected to the first, the second, and the third thin film transistors,

wherein the second sub-pixel electrode is capacitively coupled to the third pixel electrode, and the second sub-pixel electrode is present in both the first and the second areas.

2. The thin film transistor array panel of claim 1, wherein the first sub-pixel electrode is capacitively coupled to the first pixel electrode.

3. The thin film transistor array panel of claim 1, wherein the second sub-pixel electrode is capacitively coupled to the first pixel electrode.

4. The thin film transistor array panel of claim 1, wherein the second sub-pixel electrode comprises a first piece disposed in the first area and a second piece disposed in the second area.

5. The thin film transistor array panel of claim 4, wherein the first sub-pixel electrode comprises a third piece disposed in the first area and a fourth piece disposed in the second area.

6. The thin film transistor array panel of claim 5, wherein the first piece is symmetrical to the second piece and the third piece is symmetrical to the fourth piece.

7. The thin film transistor array panel of claim 5, wherein the first piece is symmetrical to the fourth piece and the second piece is symmetrical to the third piece.

8. The thin film transistor array panel of claim 5, wherein the first piece and the third piece are separated by a first cutout including an oblique portion which is oblique relative to the data line, and the second piece and the fourth piece are separated by a second cutout including an oblique portion which is oblique relative to the data line.

9. The thin film transistor array panel of claim 8, wherein each of the first and the second cutouts further includes a longitudinal portion connected to the oblique portion and substantially parallel to the data line.

10. The thin film transistor array panel of claim 8, wherein each of the first and the second cutouts has a width of at least about one micron and at most about 50 microns.

11. The thin film transistor array panel of claim 8, wherein each of the oblique portions makes an angle of 30°

to 60°

with the data line.

12. The thin film transistor array panel of claim 8, wherein at least one of the first, second, third and fourth pieces has a chamfered corner.

13. The thin film transistor array panel of claim 8, wherein at least one of the first, second, third and fourth pieces has a chamfered corner having an oblique edge substantially parallel to the oblique portions of the first and the second cutouts.

14. The thin film transistor array panel of claim 1, further comprising a coupling electrode that is connected to the second sub-pixel electrode and overlaps the third pixel electrode.

15. The thin film transistor array panel of claim 1, further comprising a storage electrode line overlapping the second pixel electrode.

16. The thin film transistor array panel of claim 1, wherein the first sub-pixel electrode and the second sub-pixel electrode have different areas.

17. The thin film transistor array panel of claim 1, wherein each of the first and third pixel electrodes comprises a first sub-pixel electrode and a second sub-pixel electrode;

wherein the thin film transistor array panel further comprises fourth, fifth, and sixth thin film transistors connected to the first sub-pixel electrodes of the first, the second, and the third pixel electrodes, respectively, and

wherein the first, the second, and the third thin film transistors are connected to the second sub-pixel electrodes of the first, the second, and the third pixel electrodes, respectively.

18. The thin film transistor array panel of claim 1, wherein the first area and the second area are located on opposite sides of the second gate line.

19. A thin film transistor array panel comprising:

first, second, and third pixel electrodes arranged sequentially, the second pixel electrode occupying an area comprising a first area and a second area that is disposed closer to the third pixel electrode than the first area;

first, second, and third thin film transistors connected to the first, the second, and the third pixel electrodes, respectively;

first, second, and third gate lines connected to the first, the second, and the third thin film transistors, respectively;

a first data line connected to the first, the second, and the third thin film transistors; and

a second data line separated from the first data line by the first, the second, and the third pixel electrodes,

wherein the second pixel electrode includes a first plurality of pieces disposed in the first area and a second plurality of pieces disposed in the second area, at least one piece of the first plurality is connected to at least one piece of the second plurality, wherein at least one piece of the second plurality is capacitively coupled to the third pixel electrode.

20. The thin film transistor array panel of claim 19, wherein at least one piece of the first plurality and at least one piece of the second plurality are adjacent to both the first and the second data lines.