Design model for a hardware device-independent method of defining embedded firmware for programmable systems

• US 20060033945A1
• Filed: 08/10/2005
• Published: 02/16/2006
• Est. Priority Date: 08/13/2004
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: McDonald, John, Ogami, Kenneth, Anderson, Doug, Pearson, Jon
• Granted Patent: US 8,286,125 B2
• Time in Patent Office: Days
• US Class Current: 358/1.130
• CPC Class Codes: G06F 8/38 for implementing user interfaces

Abstract

A processing device programming system automatically provides a user interface comprising a selectable list of one or more processing devices based on a system level solution, automatically generates an embedded programmable system solution from the system level solution and a processing device selected from the selectable list of one or more processing devices, and automatically programs the processing device according to the embedded programmable system solution.

Claims

1. A method, comprising:

automatically providing a user interface comprising a selectable list of one or more processing devices based on a system level solution;

automatically generating an embedded programmable system solution from the system level solution and a processing device selected from the selectable list of one or more processing devices; and

automatically programming the processing device according to the embedded programmable system solution.

2. The method of claim 1, wherein prior to the automatically providing, determining the selection of one or more processing devices by matching resource requirements of one or more functions of the system level solution to one or more base projects associated with the one or more processing devices.

3. The method of claim 1, further comprising automatically generating one or more base projects associated with the one or more processing devices based upon the resource requirements of the one or more functions of the system level solution and physical parameters associated with the one or more processing devices.

4. The method of claim 1, wherein prior to the automatically generating, providing the user interface with a selectable list of a plurality of high level devices to design the system level solution.

5. The method of claim 4, further comprising updating the selectable list of the plurality of high level devices and the selectable list of the one or more processing devices after each selection of a high level device from the plurality of high level devices.

6. The method of claim 5, wherein prior to updating the selectable list of the plurality of high level devices and the selectable list of the one or more processing devices, validating a current state of the system level solution.

7. The method of claim 6, wherein validating the current state of the system level solution further comprises:

validating executable expressions associated with the selected high level devices; and

validating the one or more processing devices by matching resources required by the current state of the system level solution to the one or more processing devices.

8. The method of claim 1, wherein the selectable list of one or more processing devices is comprised of at least one of a programmable logic device, a field programmable gate array, a micro-controller, a microprocessor-based device, or a circuit comprising a processing device.

9. A system, comprising:

a processing device maker engine to provide a user interface comprising a selectable list of one or more processing devices based on a system level solution; and

a hardware designer engine to receive the system level solution from the processing device maker and to generate an embedded programmable system solution from the system level solution and a processing device selected from the one or more processing devices, and to program the processing device according to the embedded programmable system solution.

10. The system of claim 9, wherein to provide the user interface, the processing device maker engine to determine the selection of one or more processing devices by matching resource requirements of one or more functions of the system level solution to one or more base projects associated with the one or more processing devices.

11. The system of claim 9, wherein the processing device maker engine further to generate one or more base projects associated with the one or more processing devices based upon the resource requirements of the one or more functions of the system level solution and physical parameters associated with the one or more processing devices.

12. The system of claim 9, wherein the processing device maker engine to provide the user interface with a selectable list of a plurality of high level devices to design the system level solution.

13. The system of claim 12, wherein the processing device maker engine to update the selectable list of the plurality of high level devices and the selectable list of the one or more processing devices after each selection of a high level device from the plurality of high level devices.

14. The system of claim 13, wherein prior to the update of the selectable list of the plurality of high level devices and the selectable list of the one or more processing devices, the processing device maker engine to validate a current state of the system level solution.

15. The system claim 14, wherein to validate the current state of the system level solution, the processing device maker engine further to validate executable expressions associated with the selected high level devices, and to validate the one or more processing devices by matching resources required by the current state of the system level solution to the one or more processing devices.

16. The system of claim 10, wherein the processing device maker engine further to save a first file comprising the system level solution, to delete one or more lower level files associated with the embedded programmable system, and to generate a schematic of the programmed selected processing device, wherein the schematic includes at least one of functional pins, input output devices, or interfacing circuitry.

17. The system of claim 10, wherein the selectable list of one or more processing devices is comprised of at least one of a programmable logic device, a field programmable gate array, a micro-controller, a microprocessor-based device, or a circuit comprising a processing device.

18. A machine readable medium having embodied thereon an instruction set, the instruction set being executable by a machine to perform operations comprising:

providing a user interface comprising a selectable list of one or more processing devices based on a system level solution;

generating an embedded programmable system solution from the system level solution and a processing device selected from the selectable list of one or more processing devices; and

programming the processing device according to the embedded programmable system solution.

19. The machine readable medium of claim 18, wherein prior to the automatically generating, providing the user interface with a selectable list of a plurality of high level devices to design the system level solution.

20. The machine readable medium of claim 19, further comprising updating the selectable list of the plurality of high level devices and the selectable list of the one or more processing devices after each selection of a high level device from the plurality of high level devices.

21. The machine readable medium of claim 20, wherein prior to updating the selectable list of the plurality of high level devices and the selectable list of the one or more processing devices, validating a current state of the system level solution.

22. The machine readable medium of claim 21, wherein validating the current state of the system level solution further comprises:

validating executable expressions associated with the selected high level devices; and

validating the one or more processing devices by matching resources required by the current state of the system level solution to the one or more processing devices.