Non-volatile memory device and erase method of the same
First Claim
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1. An erase method of a non-volatile memory device including memory cells arranged in a matrix of rows and columns, the erase method comprising:
- erasing the memory cells at the same time; and
performing an erase-verify operation for the erased memory cells, wherein the erase-verify operation is repeated under different bias conditions of the rows.
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Abstract
An erase method of a non-volatile memory device including memory cells arranged in a matrix of rows and columns. The memory cells are erased at the same time. An erase-verify operation is performed for the erased memory cells. The erase method is repeated under different bias conditions of the rows. An erase-verify operation is successively performed twice or more under different bias conditions of wordlines to decrease cell current caused by a weak cell which may be produced in a process. Thus, a reliability of an erase-verify operation is enhance to increase a yield.
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Citations
33 Claims
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1. An erase method of a non-volatile memory device including memory cells arranged in a matrix of rows and columns, the erase method comprising:
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erasing the memory cells at the same time; and
performing an erase-verify operation for the erased memory cells, wherein the erase-verify operation is repeated under different bias conditions of the rows. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An erase method of a non-volatile memory device including a plurality of cell strings each having a first select transistor connected to a string select line, a second select transistor connected to a ground select line, and memory cells being serially coupled between the first and the second select transistors, and each being connected to corresponding wordlines, the erase method comprising:
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erasing the memory cells at the same time;
performing a first erase-verify operation while a first read voltage is applied to a part of the wordlines and a second read voltage higher than the first read voltage is applied to another part of the wordlines; and
performing a second erase-verify operation while the second read voltage is applied to the part of the wordlines and the first read voltage is applied to the another part of the wordlines. - View Dependent Claims (11, 12, 13, 14, 15)
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16. An erase method of a non-volatile memory device including a plurality of cell strings each having a first select transistor connected to a string select line, a second select transistor connected to a ground select line, and memory cells being serially coupled between the first and the second select transistors, and each being connected to corresponding wordlines, the erase method comprising:
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performing a first erase-verify operation while a first read voltage is applied to first ones of the wordlines and a second read voltage higher than the first read voltage is applied to second ones of the wordlines;
performing a second erase-verify operation while the second read voltage is applied to the first ones of the wordlines and the first read voltage is applied to the second ones of the wordlines; and
judging an erase operation of the memory cells according to results of the first and the second erase-verify operations. - View Dependent Claims (17, 18, 19, 20, 21)
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22. A non-volatile memory device comprising:
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a string select line connected to a string select transistor;
a ground select line connected to a ground select transistor;
wordlines connected to memory cells and divided into at least two groups;
a row decoder circuit configured to control the wordlines and the string select line and the ground select line; and
an erase controller to control the row decoder circuit so that the wordlines of a first group of the wordlines are set to a different bias condition than the wordlines of a second group of the wordlines, in respective first and second erase-verify operations. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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29. An erase method of a non-volatile memory device including a plurality of cell strings each having a first select transistor connected to a string select line, a second select transistor connected to a ground select line, and memory cells being connected in series between the first and the second select transistors, and each being connected to corresponding wordlines, the erase method comprising:
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applying a first voltage to a gate of the first select transistor;
applying the first voltage to a gate of the second select transistor;
supplying a sensing current to a drain of the first select transistor; and
applying a second voltage higher than 0V to respective control gates of the memory cells. - View Dependent Claims (30, 31)
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32. An erase method of a non-volatile memory device including memory cells arranged in a matrix of rows and columns, the erase method comprising:
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erasing the memory cells at the same; and
performing an erase-verify operation for the erased memory cells, wherein a higher voltage than 0V is applied to each of the rows during the erase-verify operation. - View Dependent Claims (33)
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Specification
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Current AssigneeSamsung Electronics Co. Ltd.
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Original AssigneeSamsung Electronics Co. Ltd.
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InventorsHan, Eui-Gyu, Han, Gyeong-Soo, Kim, Kil-Yeon
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current365/185.290
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CPC Class CodesG11C 16/0483 comprising cells having sev...G11C 16/16 for erasing blocks, e.g. ar...G11C 16/344 Arrangements for verifying ...G11C 16/3445 Circuits or methods to veri...
