Apparatus of ion sensitive thin film transistor and method of manufacturing of the same

• US 20060035400A1
• Filed: 12/03/2004
• Published: 02/16/2006
• Est. Priority Date: 10/08/2004
• Status: Abandoned Application

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Wu, Yung Fu, Tsai, Tzu Hsuan
• Application Number:
  US11/002,282
• Publication Number:
  US 20060035400A1
• Time in Patent Office: Days
• US Class Current: 438/49
• CPC Class Codes: G01N 27/414 Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
• CPC Class Codes: H01L 27/14692 Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 31/115 Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation
• CPC Class Codes: H01L 31/202 including only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

The present invention discloses an apparatus of ion sensitive thin film transistor and method of manufacturing of the same. The apparatus of the invention, formed on a glass substrate, comprises an ion detector, formed on said glass substrate, including a plurality of ion sensitive transistors and a signal processor with display, also formed on said glass substrate, being coupled with said ion detector. The signal processor with display further comprises a circuit of signal processing, a driver circuit, and a display, wherein by means of the method of Low Temperature PolySilicon, i.e. LTPS technology, the invention integrates said ion detector and said signal processor with display on said glass substrate to become an tiny, light and thin apparatus with portable and disposable characteristics.

Claims

1. An ion sensitive thin film transistor apparatus, comprising:

a glass substrate;

an ion detector, formed on said glass substrate, including a plurality of ion sensitive sensors; and

a signal processor with display formed on said glass and coupled with said ion detector.

2. The apparatus as claimed of claim 1, wherein the said signal processor with display further comprising:

a circuit of signal processing, formed on said glass substrate and being coupled with said ion detector;

a driver circuit formed, on said glass substrate and being coupled with said circuit of signal processing; and

a display formed on said glass substrate and being coupled with said driver circuit.

3. The apparatus as claimed of claim 1, wherein the said ion detector further comprising:

a buffer layer formed on the surface of said glass substrate;

an active layer, formed on the surface of said buffer layer, further including a pair of source/drains separated from a channel region;

a layer of gate oxide, formed on the surface of said active layer, further including contact holes on said layer of gate oxide set opposite to said pair of source/drains;

a metal layer formed on the surface of said layer of gate oxide filling said contact hole to from a pair of electrodes for said pair of source/drains;

a passivation layer, formed on the surface of said metal layer, further including a probe area; and

a sensitive membrane, formed on said passivation layer, covering said probe area.

4. The apparatus as claimed of claim 3, wherein said buffer layer is substantially an oxide layer.

5. The apparatus as claimed of claim 3, wherein said pair of source/drains are selected from the group consisting of N-type doping and P-type doping.

6. The apparatus as claimed of claim 3, wherein said sensitive membrane is selected from the group consisting of enzyme membrane, SiO₂, oxide of silicon, Al₃O₂, TiO₂ and TaO_x, oxide of tantalum.

7. The apparatus as claimed of claim 3, wherein said passivation layer is a kind of material with low-k dielectric.

8. The apparatus as claimed of claim 3, wherein the top of said channel region is selected from the group consisting of retaining said metal layer and removing said metal layer.

9. An ion sensitive thin film transistor, comprising:

a glass substrate;

a buffer layer formed on the surface of said glass substrate;

an active layer, formed on the surface of said buffer layer, further including a pair of source/drains separated from a channel region;

a layer of gate oxide, formed on the surface of said active layer, further including contact holes on said layer of gate oxide set opposite to said pair of source/drains;

a metal layer formed on the surface of said layer of gate oxide filling said contact hole to from a pair of electrodes for said pair of source/drains;

a passivation layer, formed on the surface of said metal layer, further including a probe area; and

a sensitive membrane, formed on said passivation layer, covering said probe area.

10. The apparatus as claimed of claim 9, wherein said buffer layer is a oxide layer.

11. The apparatus as claimed of claim 9, wherein said pair of source/drains are selected from the group consisting of N-type doping and P-type doping.

12. The apparatus as claimed of claim 9, wherein said sensitive membrane is selected from the group consisting of enzyme membrane, SiO₂, oxide of silicon, Al₃O₂, TiO₂ and TaO_x, oxide of tantalum.

13. The apparatus as claimed of claim 9, wherein said passivation layer is a kind of material with low-k dielectric.

14. The apparatus as claimed of claim 9, wherein the top of said channel region is selected from the group consisting of retaining said metal layer and removing said metal layer.

15. A method of manufacturing an ion sensitive thin film transistor comprising the steps of:

(a) providing a glass substrate and forming a buffer layer on said glass substrate;

(b) forming an amorphous layer on said buffer layer and transforming said amorphous layer into poly-silicon layer with high temperature annealing;

(c) forming a pair of source/drains on said poly-silicon layer;

(d) forming a layer of gate oxide on said poly-silicon layer and opening contact holes on said layer of gate oxide opposite said pair of source/drains;

(e) forming a metal layer on said layer of gate oxide and filling said contact hole for form a transistor;

(f) forming a passivation layer with a probe area on said transistor; and

(g) covering said probe area with a sensitive membrane formed on said passivation layer.

16. The method as claimed of claim 15, wherein said buffer layer is a oxide layer.

17. The method as claimed of claim 15, wherein said pair of source/drains are selected from the group consisting of N-type doping and P-type doping.

18. The method as claimed of claim 15, wherein said pair of source/drains is separated from a channel region.

19. The method as claimed of claim 18, wherein the top of said channel region is selected from the group consisting of retaining said metal layer and removing said metal layer.