Ion-sensitive field effect transistor and method for producing an ion-sensitive field effect transistor

• US 20060035420A1
• Filed: 08/24/2005
• Published: 02/16/2006
• Est. Priority Date: 03/07/2003
• Status: Active Grant

• Current Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Original Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Inventors: Kurth, Eberhard, Kunath, Christian
• Granted Patent: US 7,321,143 B2
• Time in Patent Office: Days
• US Class Current: 438/151
• CPC Class Codes: G01N 27/333 Ion-selective electrodes or membranes glass electrodes G01N27/36
• CPC Class Codes: G01N 27/414 Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS

Abstract

An ion-sensitive field effect transistor includes a substrate on which there are formed a source region and a drain region. Above a channel region, the ion-sensitive field effect transistor has a gate with a sensitive layer including a metal oxide nitride mixture and/or a metal oxide nitride mixture compound.

Claims

1. An ion-sensitive field effect transistor with a gate comprising a sensitive layer, wherein the sensitive layer comprises a metal oxide nitride mixture and/or a metal oxide nitride mixture compound.

2. The ion-sensitive field effect transistor of claim 1, wherein the metal oxide nitride mixture is a hafnium tantalum oxide nitride mixture and the metal oxide nitride mixture compound is a hafnium tantalum oxide nitride mixture compound.

3. The ion-sensitive field effect transistor of claim 1, wherein the metal oxide nitride mixture is a zirconium tantalum oxide nitride mixture and the metal oxide nitride mixture compound is a zirconium tantalum oxide nitride mixture compound.

4. The ion-sensitive field effect transistor of claim 1, wherein the sensitive layer is deposited directly on a channel region of a substrate or directly on a gate isolation layer.

5. The ion-sensitive field effect transistor of claim 1, wherein, for compensating different expansion coefficients, one or more adaptation layers are deposited between the substrate and the sensitive layer, which preferably include metal oxide silicates and/or metal oxide nitride silicates.

6. A method for producing an ion-sensitive field effect transistor, comprising:

providing a substrate with a source region and a drain region; and

providing a gate with a sensitive layer, wherein the sensitive layer includes a metal oxide nitride mixture and/or a metal oxide nitride mixture compound.

7. The method of claim 6, wherein the sensitive layer is generated by sputtering or by chemical gas phase deposition.

8. The method of claim 6, wherein the sensitive layer is generated by means of the following steps:

sputtering a metal; and

performing an oxidation and a nitridization of the metal.

9. The method of claim 6, further comprising the step of tempering the sensitive layer for adjusting sensor properties.

10. The method of claim 6, wherein generating the sensitive layer is generated by adjusting parameters in depositing and/or post-treating the sensitive layer such that its structure is between amorphous and nanocrystalline.

11. The method of claim 6, further comprising the step of generating interface layers between the substrate and the sensitive layer for adapting their respective expansion coefficients.

12. The method of claim 11, wherein the interface layers include metal oxide silicates and/or metal oxide nitride silicates.

13. The method of claim 11, wherein generating interface layers is performed by means of tempering, sputtering or chemical gas phase deposition.