Storage switch task processing synchronization

• US 20060036769A1
• Filed: 04/30/2004
• Published: 02/16/2006
• Est. Priority Date: 04/30/2004
• Status: Active Grant

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Zhang, Chao, Frey, Robert Tower
• Granted Patent: US 8,171,170 B2
• Time in Patent Office: Days
• US Class Current: 709/248
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/0635 by changing the path, e.g. traffic rerouting, path reconfiguration
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]

Abstract

Systems and methods in accordance with various embodiments relate to a storage switch including task processing synchronization. In embodiments of the present invention, the packet processing units may generate and store Task Index and Generation Count information that prevents the processing of expired commands or responses. Additionally or alternatively, embodiments of the present invention may further employ timeout sequences to prevent previous instances of a stale task resource from disrupting the current use of the task resource.

Claims

1. A method of maintaining task synchronization between first and second processors within a switch of a network, comprising the steps of:

(a) provisioning information upon receipt of a data unit to be routed through the first and second processors, the information uniquely identifying the data unit; and

(b) using the information to maintain a synchronized state between the first and second processors.

2. A method of maintaining task synchronization between first and second processors as recited in claim 1, wherein the information comprises an identifier and a counter.

3. A method of maintaining task synchronization between first and second processors as recited in claim 1, wherein the data unit relates to performing a read operation, a write operation or a verify operation.

4. A method of maintaining task synchronization between first and second processors as recited in claim 1, further comprising the steps of:

(c) provisioning a timeout period within at least one of the first and second processors; and

(d) using the timeout period to maintain a synchronized state between the first and second processors.

5. A method of maintaining task synchronization between first and second processors as recited in claim 1, wherein the data unit is in a Fiber Channel IU.

6. A method of maintaining task synchronization between first and second processors as recited in claim 1, wherein the data unit is in an iSCSI PDU.

7. A method of maintaining task synchronization between first and second processors as recited in claim 1, wherein said step (b) of using the information to maintain a synchronized state between the first and second processors comprises the steps of:

(c) storing the information in memory associated with the first processor;

(d) sending the data unit with the information from the first processor to the second processor, the first processor capable of altering the information upon receipt of a new data unit thereafter;

(e) returning a response relating to the data unit from the second processor to the first processor, the response including the information;

(f) comparing the returned information with the information stored in memory; and

(g) discarding the response if the returned information and stored information are different.

8. A method of maintaining task synchronization within a switch of a network, comprising the steps of:

(a) generating information uniquely representing a task upon receipt of the task at a time t₁, the information capable of changing upon receipt of subsequent tasks;

(b) associating the information generated in said step (a) with a response generated in response to the task at a time t₂ after time t₁; and

(c) comparing the information associated with the response in said step (b) with the information generated in said step (a).

9. A method of maintaining task synchronization within a switch of a network as recited in claim 8, further comprising a step (d) of discarding the response generated in said step (b) if the information associated with the response in said step (b) is different than the information generated in said step (a).

10. A method of maintaining task synchronization within a switch of a network as recited in claim 8, wherein the unique information comprises an identifier and a counter.

11. A method of maintaining task synchronization between first and second processors within a switch of a network, comprising the steps of:

(a) generating a count upon receipt of a task from an initiator at a time t₁, the count capable of incrementing thereafter;

(b) maintaining the count generated at time t₁ in said step (a);

(c) associating the count generated at time t₁ in said step (a) with a response generated by a target in response to the task at a time t₂ after the time t₁; and

(d) comparing the count associated with the response in said step (c) with the count maintained in said step (b).

12. A method of maintaining task synchronization between first and second processors as recited in claim 11, the task comprising one of performing a read operation, a write operation or a verify operation.

13. A method of maintaining task synchronization between first and second processors as recited in claim 11, wherein the task is communicated in one of iSCSI or Fibre Channel protocols.

14. A method of maintaining task synchronization between first and second processors as recited in claim 11, wherein the first processor is in communication with an initiator.

15. A method of maintaining task synchronization between first and second processors as recited in claim 14, wherein the initiator is a server.

16. A method of maintaining task synchronization between first and second processors as recited in claim 11, wherein the second processor is in communication with a target.

17. A method of maintaining task synchronization between first and second processors as recited in claim 16, wherein the target is one or more physical storage devices.

18. A method of maintaining task synchronization between first and second processors as recited in claim 11, wherein a data unit relating to the task is routed between the first and second processors through the fabric of the switch.

19. A method of maintaining task synchronization between first and second processors within a switch of a network, the first and second processors capable of routing a data unit between an initiator of the data unit and a target for the data unit, the method comprising the steps of:

(a) provisioning an identifier identifying the data unit at a time t₁;

(b) provisioning a count further identifying data unit at the time t₁, the count capable of incrementing thereafter;

(c) storing the identifier and count provisioned at time t₁ in said steps (a) and (b);

(d) associating the identifier and the count provisioned at time t₁ in said steps

(a) and (b) with a response generated within the second processor in response to the task at time t₂ after the time t₁; and

(e) comparing the count associated with the response in said step (d) with the count stored in said step (c).

20. A method of maintaining task synchronization between first and second processors as recited in claim 19, the task comprising one of performing a read operation, a write operation or a verify operation.

21. A method of maintaining task synchronization between first and second processors as recited in claim 19, wherein the task is communicated in one of iSCSI or Fibre Channel protocols.

22. A method of maintaining task synchronization between first and second processors as recited in claim 19, further comprising the step of discarding the response generated in said step (d) if the count associated with the response in said step (d) is not the same as the count stored in said step (c).

23. A method of maintaining task synchronization between first and second processors as recited in claim 19, further comprising the step of releasing any resources allocated for the response generated in said step (d) if the count associated with the response in said step (d) is not the same as the count stored in said step (c).

24. A method of maintaining task synchronization between first and second processors as recited in claim 19, further comprising the step of informing the initiator of the result if the count associated with the response in said step (d) is not the same as the count stored in said step (c).

25. A system of maintaining task synchronization between first and second processors within a switch of a network, the system comprising:

means for provisioning information upon receipt of a data unit to be routed through the first and second processors, the information uniquely identifying the data unit; and

means for using the information to maintain a synchronized state between the first and second processors.

26. A system of maintaining task synchronization between first and second processors as recited in claim 25, wherein the information comprises an identifier and a counter.

27. A system of maintaining task synchronization between first and second processors as recited in claim 25, wherein the data unit relates to performing a read operation, a write operation or a verify operation.

28. A system of maintaining task synchronization between first and second processors as recited in claim 25, further comprising:

means for provisioning a timeout period within at least one of the first and second processors; and

means for using the timeout period to maintain a synchronized state between the first and second processors.

29. A system of maintaining task synchronization between first and second processors as recited in claim 25, wherein the data unit is in a Fiber Channel IU.

30. A system of maintaining task synchronization between first and second processors as recited in claim 25, wherein the data unit is in an iSCSI PDU.

31. A system of maintaining task synchronization between first and second processors as recited in claim 25, said means of using the information to maintain a synchronized state between the first and second processors comprising:

storing the information in memory associated with the first processor;

sending the data unit with the information from the first processor to the second processor, the first processor capable of altering the information upon receipt of a new data unit thereafter;

returning a response relating to the data unit from the second processor to the first processor, the response including the information;

comparing the returned information with the information stored in memory; and

discarding the response if the returned information and stored information are different.

32. A method of maintaining task synchronization between first and second processors capable of routing a data unit through a switch of a network, comprising the steps of:

(a) provisioning a timeout period within at least one of the first and second processors; and

(b) using the timeout period to maintain a synchronized state between the first and second processors.

33. A method of maintaining task synchronization between first and second processors as recited in claim 32, said step of using the timeout period to maintain a synchronized state between the first and second processors comprising the steps of:

(c) monitoring the passage of the timeout period;

(d) resetting the timeout period to its initial state if a response to a communication from the first processor to the second processor is received back in the first processor before expiration of the timeout period; and

(d) discarding a response from the second processor to the first processor if the response is received after expiration of the timeout period.

34. A method of maintaining task synchronization between first and second processors within a switch of a storage area network, the first and second processors capable of routing a task between an initiator of the task and a target for the task, the method comprising the steps of:

(a) monitoring the passage of a first period of time in the first processor;

(b) resetting the first period of time to its initial state if the first processor receives a response to a communication it sent before expiration of the first period of time;

(c) monitoring the passage of a second period of time in the second processor;

(d) resetting the second period of time to its initial state if the second processor receives a response to a communication it sent before expiration of the second period of time; and

(e) discarding a response if the response is received after elapse of the first period of time or the second period of time.

35. A method of maintaining task synchronization between first and second processors within a switch of a storage area network, the first and second processors capable of routing a task between an initiator of the task and a target for the task, the method comprising the steps of:

(a) receiving in the first processor a command from the initiator to perform the task;

(b) routing the command to the second processor for forwarding to the target;

(c) monitoring the passage of a first period of time in the first processor;

(d) resetting the first period of time to its initial state if the first processor receives a response to a communication it sent before expiration of the first period of time;

(e) monitoring the passage of a second period of time in the second processor;

(f) resetting the second period of time to its initial state if the second processor receives a response to a communication it sent before expiration of the second period of time; and

(g) discarding a response to the task from the target if the response is received after elapse of the first period of time or the second period of time.

36. A method of maintaining task synchronization between first and second processors as recited in claim 35, wherein the first period of time monitored for the second processor is shorter than the period of time monitored for the first processor.

37. A method of maintaining task synchronization between first and second processors as recited in claim 35, wherein the first and second periods of time are shorter than a third period of time, the elapse of which third period of time without receiving a response causes the initiator to timeout.