Deterring theft and unauthorized use of electronic devices

• US 20060036781A1
• Filed: 08/16/2004
• Published: 02/16/2006
• Est. Priority Date: 08/16/2004
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Thacker, Charles P.
• Granted Patent: US 7,571,265 B2
• Time in Patent Office: Days
• US Class Current: 710/36
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/88 Detecting or preventing theft or loss

Abstract

A system and method are provided for reducing a potential thief'"'"'s motivation to steal an electronic device, by rendering the device inoperative at some time after it is stolen. The mechanism used to deter theft may include a modified primary integrated circuit chip in the electronic device, such as the central processing unit (CPU), a memory controller chip, or a primary input/output (I/O) chip. The chip may be important enough to the normal operation of the electronic device such that without normal operation of the chip, the electronic device also would not operate normally, thus rendering the electronic device partially or fully disabled. A “recharger” device may be used to recharge, or reset the operability of the chip.

Claims

1. An apparatus, comprising an integrated circuit that includes disabling circuitry, the disabling circuitry having a first counter, wherein the disabling circuitry is configured to selectively disable the integrated circuit responsive to a first count state defined by the first counter reaching a first defined value.

2. The apparatus of claim 1, wherein the apparatus is an electronic device, the integrated circuit being required for operation of the electronic device.

3. The apparatus of claim 1, wherein the integrated circuit includes a microprocessor.

4. The apparatus of claim 1, wherein the integrated circuit includes a memory controller.

5. The apparatus of claim 1, wherein the integrated circuit includes an input-output controller.

6. The apparatus of claim 1, wherein the integrated circuit includes a bus controller.

7. The apparatus of claim 1, wherein the integrated circuit further includes an oscillator coupled to the first counter, wherein the first counter is configured to change the first count state responsive to the oscillator.

8. The apparatus of claim 1, wherein the first counter maintains the first count state when power is removed from the integrated circuit.

9. The apparatus of claim 1, wherein the integrated circuit further includes an external data connection configured to receive external data, and the disabling circuitry is configured to compare at least a portion of the external data with internal data stored in the integrated circuit and to set the first count state of the first counter based on the comparison.

10. The apparatus of claim 9, wherein the disabling circuitry is configured to set the first count state to a value that is defined by the external data.

11. The apparatus of claim 1, wherein the integrated circuit further includes an external data connection to receive external data, and the disabling circuitry is further configured to compare the external data with internal data stored in the integrated circuit and to enable the integrated circuit based on the comparison.

12. The apparatus of claim 1, wherein the integrated circuit further includes an external data connection to send and receive data, and the disabling circuitry is configured to send first internal data stored in the integrated circuit to the external data connection, receive external data from the external data connection, compare the external data with second internal data stored in the integrated circuit, and enable the integrated circuit based on the comparison.

13. The apparatus of claim 1, wherein the disabling circuitry further includes a second counter defining a second count value and a storage element, and wherein the integrated circuit further includes an external data connection to send and receive data, wherein the disabling circuitry is configured to send a content of the storage element to the external data connection only a predetermined number of times based on the second count value.

14. The apparatus of claim 1, wherein the integrated circuit has a chip data connection, the apparatus further including a housing, a data communication port accessible from outside the housing, and a dedicated data transmission path coupling the chip data connection with the data communication port.

15. In an integrated circuit having a counter and disabling circuitry, a method comprising steps of:

the counter counting to a defined value; and

responsive to the defined value being reached, the disabling circuitry disabling the integrated circuit.

16. The method of claim 15, further comprising steps of:

sending first internal data stored in the integrated circuit out through an external data connection of the integrated circuit;

receiving external data into the external data connection; and

comparing the external data with second internal data stored in the integrated circuit.

17. The method of claim 16, further comprising a step of setting the counter to a second defined value responsive to the comparison.

18. The method of claim 17, wherein the step of setting is performed responsive to the external data and the internal data being identical.

19. The method of claim 17, wherein the step of setting the counter includes receiving the second defined value from the external data connection.

20. The method of claim 17, wherein the second defined value is received from a storage element of the integrated circuit.

21. The method of claim 15, wherein the step of counting is performed responsive to an output of an oscillator of the integrated circuit.