Apparatus and method for dynamically repairing a semiconductor memory

• US 20060036921A1
• Filed: 08/16/2005
• Published: 02/16/2006
• Est. Priority Date: 07/18/2002
• Status: Active Grant

• Current Assignee: Aaron M. Baum, Brian P. Callaway
• Original Assignee: Aaron M. Baum, Brian P. Callaway
• Inventors: Callaway, Brian P., Baum, Aaron M.
• Granted Patent: US 7,212,456 B2
• Time in Patent Office: Days
• US Class Current: 714/736
• CPC Class Codes: G11C 2029/2602 Concurrent test
• CPC Class Codes: G11C 2029/3602 Pattern generator
• CPC Class Codes: G11C 2029/4002 Comparison of products, i.e. test results of chips or with golden chip
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/28 Dependent multiple arrays, e.g. multi-bit arrays
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/785 with redundancy programming schemes

Abstract

An architecture for dynamically repairing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), includes circuitry for dynamically storing memory element remapping information. Memory is tested for errors by writing, then reading a plurality of memory blocks, such as rows or columns, in parallel. Memory is dynamically reprogrammed in order to remap unused spare memory elements for failed memory elements when errors are detected. Unused spare memory elements are remapped utilizing a circuit that overrides unblown fuses or antifuses.

Claims

1. A semiconductor memory including a capability for testing for memory faults, comprising:

a first memory block comprising a first plurality of bits of memory;

a second memory block comprising a second plurality of bits of memory; and

a test circuit configured for;

writing a pattern of bits to the first memory block and the second memory block;

reading a first plurality of read bits from the first memory block;

reading a second plurality of read bits from the second memory block; and

comparing each one of the first plurality of read bits with a corresponding one of the second plurality of read bits.