Device and method for extracting parasitic capacitance of semiconductor circuit

• US 20060036984A1
• Filed: 01/11/2005
• Published: 02/16/2006
• Est. Priority Date: 08/13/2004
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Mukaihira, Kazunobu
• Application Number:
  US11/032,187
• Publication Number:
  US 20060036984A1
• Time in Patent Office: Days
• US Class Current: 716/115
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A device for extracting parasitic capacitance including the influence of a dummy metal pattern inserted between the circuit wires of a semiconductor device comprises a permittivity correction unit for correcting the permittivity of a dielectric existing between the circuit wires in accordance with the insertion of the dummy metal and a parasitic capacitance extraction unit for extracting parasitic capacitance between the circuit wires, based on the corrected permittivity and the layout of a circuit.

Claims

1. A device for extracting parasitic capacitance including the influence of a dummy metal pattern inserted between the circuit wires of a semiconductor device, comprising:

a permittivity correction unit for correcting the permittivity of a dielectric existing between the circuit wires in accordance with the insertion of the dummy metal; and

a parasitic capacitance extraction unit for extracting parasitic capacitance between the circuit wires, based on the corrected permittivity and the layout of a circuit.

2. The device according to claim 1, wherein

said permittivity correction unit corrects permittivity by handling a dummy metal forming the dummy metal pattern as a dielectric with infinite permittivity.

3. The device according to claim 1, wherein

said permittivity correction unit corrects permittivity, using the surface density of an area between wires of a dummy metal forming the dummy metal pattern inserted between the circuit wires.

4. The device according to claim 1, wherein

said parasitic capacitance extraction unit extracts parasitic capacitance existing between the circuit wires by applying permittivity before the correction to a dielectric area adjacent to the circuit wires within a distance corresponding to a design minimum space between the circuit wires and the dummy metal pattern and applying permittivity after the correction to dielectric areas other than the adjacent dielectric area, based on the generation rules of a dummy medal pattern.

5. A method for extracting parasitic capacitance including the influence of a dummy metal pattern inserted between the circuit wires of a semiconductor device, comprising:

calculating the correction value of the permittivity of a dielectric existing between the circuit wires in accordance the insertion of the dummy metal pattern; and

extracting parasitic capacitance between the circuit wires, based on the correction value of permittivity and the layout of a circuit.

6. The method according to claim 5, wherein

the correction value of permittivity is calculated by handling a dummy metal forming the dummy metal pattern as a dielectric with infinite permittivity.

7. The method according to claim 5, wherein

the correction value of permittivity is calculated using the surface density of an area between wires of a dummy metal forming the dummy metal pattern inserted between the circuit wires.

8. The method according to claim 5, wherein

the parasitic capacitance existing between the circuit wires is calculated by applying permittivity before the correction to a dielectric area adjacent to the circuit wires within a distance corresponding to a design minimum space between the circuit wires and the dummy metal pattern and applying permittivity after the correction to dielectric areas other than the adjacent dielectric area, based on the generation rules of a dummy medal pattern.

9. A computer-readable storage medium on which is recorded a program for enabling a computer to extract parasitic capacitance including the influence of a dummy metal pattern inserted between the circuit wires of a semiconductor device, said program comprising:

calculating the correction value of the permittivity of a dielectric existing between the circuit wires in accordance the insertion of the dummy metal pattern; and

extracting parasitic capacitance between the circuit wires, based on the correction value of permittivity and the layout of a circuit.

10. The storage medium according to claim 9, wherein

the correction value of permittivity is calculated by handling a dummy metal forming the dummy metal pattern as a dielectric with infinite permittivity.

11. The storage medium according to claim 9, wherein

the correction value of permittivity is calculated using the surface density of an area between wires of a dummy metal forming the dummy metal pattern inserted between the circuit wires.

12. The storage medium according to claim 9, wherein

the parasitic capacitance existing between the circuit wires is calculated by applying permittivity before the correction to a dielectric area adjacent to the circuit wires within a distance corresponding to a design minimum space between the circuit wires and the dummy metal pattern and applying permittivity after the correction to dielectric areas other than the adjacent dielectric area, based on the generation rules of a dummy medal pattern.