Manufacturing process of thin film transistor liquid crystal display

• US 20060038181A1
• Filed: 08/17/2005
• Published: 02/23/2006
• Est. Priority Date: 10/12/2000
• Status: Abandoned Application

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Tseng, Shiuh-Ping
• Application Number:
  US11/207,012
• Publication Number:
  US 20060038181A1
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A process for manufacturing a thin film transistor liquid crystal display (TFT-LCD) is disclosed. The process can reduce the number of the mask used in the photolithography process to three masks, form a capacitor during the manufacturing process simultaneously, and enhance the transmission rate of the TFT-LCD. Because the pixel electrodes are formed directly on the substrate, without forming an insulator layer in the pixel area, the transmission can be enhanced. The manufacturing process also provides a protective circuit for avoiding electrostatic discharge damage, and a passivation layer to protect the capacitor, the gate line, and the signal line.

Claims

1-11. -11. (canceled)

12. A thin film transistor liquid crystal display, comprising:

a substrate comprising a thin film transistor and a capacitor disposed thereon; and

a signal line comprising;

a signal insulating layer formed on the substrate;

a signal semiconductor layer and a signal doped silicon layer formed on the signal insulating layer;

a signal metal layer formed on the signal doped silicon layer; and

a signal transparent conducting layer formed on the signal metal layer, wherein the signal transparent conducting layer has the same pattern with the signal metal layer in the signal line.

13. The thin film transistor liquid crystal display as claimed in claim 12, wherein a side wall of the signal transparent conducting layer sidewall is substantially aligned to a sidewall of the signal metal layer.

14. The thin film transistor liquid crystal display as claimed in claim 12, further comprising an ESD protective circuit disposed on the substrate, wherein the ESD protective circuit comprises:

a gate line disposed on and contacting the substrate; and

a transparent conducting layer contacting the gate line, the signal metal layer of the signal line, and a sidewall of the signal line.

15. The thin film transistor liquid crystal display as claimed in claim 12, further comprising a passivation layer covering the thin film transistor.

16. The thin film transistor liquid crystal display as claimed in claim 12, further comprising a transparent pixel electrode contacting the substrate.

17. A thin film transistor liquid crystal display, comprising:

a substrate;

a thin film transistor comprising;

a gate electrode formed on the substrate;

a transistor insulating layer and a transistor semiconductor layer formed on the gate electrode;

a first doped silicon layer and a second doped silicon layer formed on the transistor semiconductor layer, the first doped silicon layer and the second doped silicon layer being separated by a channel area;

a source metal layer and a source transparent conducting layer formed on the first doped silicon layer; and

a drain metal layer and a drain transparent conducting layer formed on the second doped layer;

a capacitor comprising;

a capacitor bottom electrode formed on the substrate;

a capacitor insulating layer and a capacitor semiconductor layer formed on the capacitor bottom electrode;

a capacitor doped silicon layer formed on the capacitor semiconductor layer; and

a capacitor metal layer and a capacitor transparent conducting layer formed on the

capacitor doped silicon layer, and the capacitor metal layer being defined as a

capacitor upper electrode; and

a signal line comprising;

a signal insulating layer formed on the substrate;

a signal semiconductor layer and a signal doped silicon layer formed on the signal insulating layer;

a signal metal layer formed on the signal doped silicon layer; and

a signal transparent conducting layer formed on the signal metal layer;

wherein a side wall of the source metal layer is substantially aligned to a sidewall of the source transparent conducting layer,

the capacitor transparent conducting layer has a first width, the capacitor metal layer has a second width, the capacitor semiconductor layer has a third width, and the first width, the second width, and the third width are substantially the same, and

the signal transparent conducting layer has the same pattern with the signal metal layer in the signal line.

18. The thin film transistor liquid crystal display as claimed in claim 17, wherein a side wall of the signal transparent conducting layer sidewall is substantially aligned to a sidewall of the signal metal layer.

19. The thin film transistor liquid crystal display as claimed in claim 17, further comprising a passivation layer covering the thin film transistor, and filling within the channel area of thin film transistor.

20. The thin film transistor liquid crystal display as claimed in claim 17, further comprising a transparent pixel electrode contacting the substrate.