MULTIPLE POWER DENSITY CHIP STRUCTURE

• US 20060038281A1
• Filed: 08/18/2004
• Published: 02/23/2006
• Est. Priority Date: 08/18/2004
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ramaswamy, Chandrashekhar, Katopis, George A., Colgan, Evan G., Stoller, Herbert I.
• Granted Patent: US 7,193,318 B2
• Time in Patent Office: Days
• US Class Current: 257/706
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3732 Diamonds
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/3738 Semiconductor materials
• CPC Class Codes: H01L 23/42 Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A multiple power density packaging structure with two or more semiconductor chips on a common wiring substrate having a common thermal spreader with a planar surface in thermal contact with the non-active surfaces of the chips. The semiconductor chips have different cooling requirements and some of the chips are thinned to insure that the chips requiring the lowest thermal resistance has the thinnest layer of a thermal adhesive or metal or solder interface between the chip and thermal spreader.

Claims

1. An electronic packaging structure comprising:

a chip carrier;

at least two semiconductor devices attached to said chip carrier, where at least one of said at least two semiconductor devices has a different thickness;

a heat spreader having a substantially planar surface in thermal contact with said at least two semiconductor devices; and

a thermal adhesive layer in contact with said heat spreader and with said at least two semiconductor devices whereby a semiconductor device requiring a lower thermal resistance has a thinner thermal adhesive layer than a semiconductor device which can tolerate a higher thermal resistance.

2. The packaging structure of claim 1 wherein said chip carrier is a ceramic chip carrier.

3. The packaging structure of claim 1 wherein said chip carrier is an organic chip carrier.

4. The packaging structure of claim 1 wherein said semiconductor devices are selected from the group consisting of integrated circuit chips, capacitors, resistors and thermistors.

5. The packaging structure of claim 1 wherein said heat spreader is comprised of material selected from the group consisting of diamond, Si, SiC, Mo, ceramic and composites containing these materials.

6. The packaging structure of claim 1 wherein said thermal adhesive layer is comprised of a material selected from the group consisting of Ag filled epoxy, filled thermoplastic, filled polymer, filled polymer adhesive, metal and solder.

7. The packaging structure of claim 1 wherein a different thermal adhesive layer is used for a semiconductor device which has a different thickness.

8. The packaging structure of claim 1 wherein said at least two semiconductor devices comprise at least one high power density semiconductor device and at least one low power density device and a compliant thermal adhesive layer material is used on said lower power density semiconductor device and a rigid thermal adhesive layer material is used on said high power density device.

9. The packaging structure of claim 1 wherein said heat spreader is the package lid.

10. The packaging structure of claim 1 further comprising a heat sink in thermal contact with said heat spreader.

12. The method of claim 1 wherein said chip carrier is a ceramic chip carrier.

13. The method of claim 1 wherein said chip carrier is an organic chip carrier.

14. The method of claim 1 wherein said semiconductor devices are selected from the group consisting of integrated circuit chips, capacitors, resistors and thermistors.

15. The method of claim 1 wherein said heat spreader is comprised of material selected from the group consisting of diamond, Si, SiC, Mo, ceramic, and composites containing these materials.

16. The method of claim 1 wherein said thermal adhesive layer is comprised of a material selected from the group consisting of Ag filled epoxy, filled thermoplastic, filled polymer, filled polymer adhesive, metal and solder.

17. The method of claim 1 wherein a different thermal adhesive layer is used for a different semiconductor device thickness.

18. The method of claim 1 wherein said at least two semiconductor devices comprise at least one high power density semiconductor device and at least one low power density device and a compliant thermal adhesive layer material is used on said lower power density semiconductor device and a rigid thermal adhesive layer material is used on said high power density device.

19. The method of claim 1 wherein said heat spreader is the package lid.

20. The method of claim 1 further comprising the step of attaching a heat sink on to said heat spreader.

11. A method for cooling multiple semiconductor devices with different cooling requirements on a common chip carrier with a common lid or heat spreader comprising the steps of:

providing a chip carrier;

attaching at least two semiconductor devices to said chip carrier, where at least one of said at least two semiconductor devices has a different thickness;

placing a heat spreader having a substantially planar surface in thermal contact with said at least two semiconductor devices; and

placing a thermal adhesive layer in contact with said heat spreader and with said at least two semiconductor devices whereby a semiconductor device requiring a lower thermal resistance has a thinner thermal adhesive layer than a semiconductor device which can tolerate a higher thermal resistance.