Integrated circuit with increased heat transfer

• US 20060038283A1
• Filed: 02/03/2005
• Published: 02/23/2006
• Est. Priority Date: 08/18/2004
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Su, Michael Zhuoying, Eppes, David Harry
• Granted Patent: US 7,259,458 B2
• Time in Patent Office: Days
• US Class Current: 257/706
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10158 at the passive surface

Abstract

A technique for improving the thermal power dissipation of an integrated circuit includes reducing the thermal resistivity of the integrated circuit by increasing heat transfer in vertical and/or lateral directions. These results are achieved by increasing the surface area of the backside and/or the surface area of the lateral sides of the integrated circuit die. In some embodiments of the invention, an integrated circuit includes circuit elements formed closer to a first surface of a semiconductor substrate than to a second surface of the semiconductor substrate. The semiconductor substrate has a varying profile that substantially increases the surface area of a thermal interface formed on the second surface as compared to the second surface being substantially planar. A maximum depth of the profile is less than the thickness of the semiconductor substrate.

Claims

1. An integrated circuit die comprising:

circuit elements formed closer to a first surface of a semiconductor substrate than to a second surface of the semiconductor substrate;

the semiconductor substrate having a varying profile, the varying profile substantially increasing the surface area of a thermal interface formed on the second surface as compared to the second surface being substantially planar; and

wherein a maximum depth of the profile is less than the thickness of the semiconductor substrate.

2. The integrated circuit die, as recited in claim 1, further comprising:

a thermally conductive layer thermally coupled to the semiconductor substrate,

the thermally conductive layer being electrically isolated from the circuit elements.

3. The integrated circuit die, as recited in claim 2, wherein the thermally conductive layer comprises an interface to ambient having a varying profile, the varying profile substantially increasing the surface area of the interface to ambient as compared to the interface to ambient being substantially planar.

4. The integrated circuit die, as recited in claim 2, wherein the thermally conductive layer has a substantially planar interface to a thermal interface material (TIM).

5. The integrated circuit die, as recited in claim 1, wherein increases in density of profile variations are based at least in part on portions of the integrated circuit generating greater thermal power than other portions of the integrated circuit.

6. The integrated circuit die, as recited in claim 2, wherein the thermally conductive layer is a thermal interface material (TIM).

7. The integrated circuit die, as recited in claim 2, further comprising:

a thermal interface material (TIM) layer adjacent to the thermally conductive layer.

8. The integrated circuit die, as recited in claim 7, further comprising:

a lid adjacent to the TIM layer.

9. An integrated circuit die comprising:

circuit elements formed closer to a first surface of a semiconductor substrate than to a second surface of the semiconductor substrate;

the semiconductor substrate having a varying profile, the varying profile substantially increasing the surface area of a thermal interface formed on the second surface as compared to the second surface being substantially planar;

a thermally conductive layer thermally coupled to the semiconductor substrate, the thermally conductive layer being electrically isolated from the circuit elements; and

wherein the thermally conductive layer interfaces a dielectric layer formed between the first surface of the semiconductor substrate and the circuit elements.

10. The integrated circuit die, as recited in claim 9, wherein the thermally conductive layer comprises an interface to ambient, the interface to ambient having a varying profile, the varying profile substantially increasing the surface area of the interface to ambient as compared to the interface to ambient being substantially planar.

11. The integrated circuit die, as recited in claim 9, further comprising:

a thermal interface material (TIM) layer adjacent to the thermally conductive layer, the thermally conductive layer having a planar interface to the TIM layer; and

a lid adjacent to the TIM layer.

12. The integrated circuit die, as recited in claim 9, wherein increases in density of profile variations of the second surface are based at least in part on portions of the integrated circuit generating greater thermal power than other portions of the integrated circuit.

13. The integrated circuit die, as recited in claim 9, wherein the thermally conductive layer is a thermal interface material.

14. A method comprising:

reducing a thermal resistivity of an integrated circuit die by increasing a surface area of a first surface of a semiconductor substrate, circuit elements being formed closer to a second surface of the semiconductor substrate than to the first surface, a maximum depth of a profile of the first surface being less than a thickness of the semiconductor substrate.

15. The method, as recited in claim 14, further comprising:

reducing the thermal resistivity of the die by thermal dissipation via a thermally conductive layer formed on the first surface.

16. The method, as recited in claim 15, further comprising:

further reducing the thermal resistivity of the die by increasing the surface area of the thermally conductive layer.

17. A method comprising:

reducing a thermal resistivity of an integrated circuit die by increasing the surface area of a first surface of a semiconductor substrate, circuit elements being formed closer to a second surface of the semiconductor substrate than to the first surface;

reducing the thermal resistivity of the die by thermal dissipation via a thermally conductive layer formed on the first side of the die; and

wherein the thermally conductive layer is electrically isolated from the circuit elements and interfaces a dielectric layer formed between the second surface of the semiconductor substrate and the circuit elements.

18. The method, as recited in claim 17, further comprising:

further reducing the thermal resistivity of the die by increasing the surface area of the thermally conductive layer.

19. The method, as recited in claim 17, wherein increases in density of a profile of the first surface are based at least in part on portions of the integrated circuit generating greater thermal power than other portions of the integrated circuit.

20. An apparatus comprising:

means for reducing a thermal resistivity of an integrated circuit die by increasing a surface area of a first surface of a semiconductor substrate, circuit elements being formed closer to a second surface of the semiconductor substrate than to the first surface, a maximum depth of a profile of the first surface being less than a thickness of the semiconductor substrate; and

means for reducing the thermal resistivity of the die by thermal dissipation via a thermally conductive layer formed on the first surface.

21. An apparatus comprising:

means for reducing a thermal resistivity of an integrated circuit die by increasing the surface area of a first surface of a semiconductor substrate, circuit elements being formed closer to a second surface of the semiconductor substrate than to the first surface;

means for reducing the thermal resistivity of the die by thermal dissipation via a thermally conductive layer formed on the first side of the die;

means for electrically isolating the thermally conductive layer from the circuit elements; and

means for interfacing a dielectric layer formed between the second surface of the semiconductor substrate and the circuit elements.

22. The apparatus, as recited in claim 21, further comprising:

means for further reducing the thermal resistivity of the die by increasing the surface area of the thermally conductive layer.

23. An integrated circuit die comprising:

at least one lateral side of the die having a varying profile, the varying profile substantially increasing the surface area of a thermal interface formed on the lateral side as compared to the lateral side being substantially planar.

24. The integrated circuit die, as recited in claim 23, further comprising:

a thermally conductive layer thermally coupled to the lateral side of the die, the thermally conductive layer being electrically isolated from the circuit elements.