Metallization performance in electronic devices

• US 20060038294A1
• Filed: 08/17/2004
• Published: 02/23/2006
• Est. Priority Date: 08/17/2004
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Ryan, Vivian, Lian, Sean, Jones, Bailey R., Molloy, Simon John, Desko, John C. Jr.
• Granted Patent: US 7,339,274 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Phenomena such as electromigration and stress-induced migration occurring in metal interconnects of devices such as integrated circuits are inhibited by use of underlying non-planarities. Thus the material underlying the interconnect is formed to have non-planarities typically of at least 0.02 μm in height and advantageously within 100 μm of another such non-planarity. Such non-planarities, it is contemplated, reduce grain boundary movement in the overlying interconnect with a concomitant reduction in void aggregation.

Claims

1. An electronic device having design rule of 0.9 μ

m or finer comprising

     1) an electrical interconnect comprising a metal having two transverse edges and

     2) a material underlying said electrical interconnect wherein the surface of said material includes non-planarities having a height of at least 0.02 μ

m such that at least 80 percent of the distances between nearest neighbors of said non-planarities that are within 0.1 μ

m of at least one of said transverse edges of said interconnect is about 100 μ

m or less.

2. The device of claim 1 wherein said metal comprises copper.

3. The device of claim 2 wherein said material comprises tantalum or tantalum nitride.

4. The device of claim 1 wherein said metal comprises aluminum.

5. The device of claim 1 wherein said material comprises titanium nitride or a silicon oxide.

6. The device of claim 1 wherein said metal comprises gold or silver.

7. The device of claim 1 wherein said non-planarities are located within 0.1 μ

m of both said transverse edges.

8. The device of claim 1 wherein said interconnect comprises a copper runner formed in a surrounding trench.

9. The device of claim 1 wherein said interconnect comprises an aluminum runner in a device that operates at temperatures of 80°

C. or more.

10. An integrated circuit including an electronic device having design rule of 0.9 μ

m or finer comprising

     1) an electrical interconnect comprising a metal having two transverse edges and

     2) a material underlying said electrical interconnect wherein the surface of said material includes non-planarities having a height of at least 0.02 μ

m such that at least 80 percent of the distances between nearest neighbors of said non-planarities that are within 0.1 μ

m of at least one of said transverse edges of said interconnect is about 100 μ

m or less.

11. The device of claim 10 wherein said metal comprises copper.

12. The device of claim 11 wherein said material comprises tantalum or tantalum nitride.

13. The device of claim 10 wherein said metal comprises aluminum.

14. The device of claim 10 wherein said metal comprises titanium nitride or a silicon oxide.

15. The device of claim 10 wherein said metal comprises gold or silver.

16. The device of claim 10 wherein said non planarities are located within 0.1 μ

m of both said transverse edges.

17. The device of claim 10 wherein said interconnect comprises a copper runner formed in a surrounding trench.

18. The device of claim 10 wherein said interconnect comprises an aluminum runner in a device that operates at temperatures of 80°

C. or more.

19. A wafer including an electronic device having design rule of 0.9 μ

m or finer comprising

     1) an electrical interconnect comprising a metal having two transverse edges and

     2) a material underlying said electrical interconnect wherein the surface of said material includes non-planarities having a height of at least 0.02 μ

m such that at least 80 percent of the distances between nearest neighbors of said non-planarities that are within 0.1 μ

m of at least one of said transverse edges of said interconnect is about 100 μ

m or less.

20. The device of claim 19 wherein said metal comprises copper.

21. The device of claim 20 wherein said metal comprises tantalum or tantalum nitride.

22. The device of claim 19 wherein said metal comprises aluminum.

23. The device of claim 19 wherein said material comprises titanium nitride or a silicon oxide.

24. The device of claim 19 wherein said metal comprises gold or silver.

25. The device of claim 19 wherein said non planarities are located within 0.1 μ

m of both said transverse edges.

26. The device of claim 19 wherein said interconnect comprises a copper runner formed in a surrounding trench.

27. The device of claim 19 wherein said interconnect comprises an aluminum runner in a device that operates at temperatures of 80°

C. or more.