Driver for swicthing circuit and drive method

• US 20060038545A1
• Filed: 11/19/2003
• Published: 02/23/2006
• Est. Priority Date: 11/29/2002
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Rutter, Philip
• Granted Patent: US 7,205,821 B2
• Time in Patent Office: Days
• US Class Current: 323/283
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 17/04206 in field-effect transistor switches
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A driver circuit includes monitoring circuitry (32, 34, 36) for monitoring the states of high and low side switches (6, 8). The driver circuit has an adjustable delay for turning on the transistors (6, 8). The delay is decreased when the monitoring circuit detects that a voltage corresponding to one transistor passes a predetermined voltage V1 before a voltage corresponding to the other transistor passes another predetermined point V2, and vice versa.

Claims

1. A drive circuit (8) for a switching circuit, comprising:

first and second gate control outputs (26, 28) for connection to the gates of respective first and second insulated gate transistors (6, 8);

first and second gate drivers (22, 24) connected to the first and second gate control outputs (26, 28) respectively for driving the respective gates to switch the first and second insulated gate transistors on and off alternately;

monitoring circuitry (32, 34, 36) for monitoring the voltages on first and second monitor points and hence the state of the first and second transistors (6, 8) respectively, the first monitor point being one of the first gate and a switch node (10) between first and second transistors and the second monitor point being the second gate;

wherein the drive circuitry is arranged;

to drive the second gate driver (24) to switch off the second insulated gate transistor (8) and then after a controllable delay D to drive the first gate driver (22) to switch on the first insulated gate transistor (6);

to compare the time that the voltage on the first monitor point passes a first predetermined voltage and the time that the voltage on the monitor point passes a second predetermined voltage; and

to decrease the delay D if the second time is before the first time and to increase the delay D if the second time is after the first time.

2. A drive circuit according to claim 1 wherein the first monitor point is the first gate control output (26) and the second monitor point is the second gate control output (28).

3. A drive circuit according to claim 1 wherein first and second insulated gate transistors are connected together in series at a switch node and the first monitor point is the switch node.

4. A drive circuit according to any preceding claim wherein every time the delay D is increased or decreased it is increased or decreased by a constant predetermined time.

5. A drive circuit according to claim 4 wherein the predetermined time is in the range 1 ns to 5 ns.

6. A drive circuit according to any preceding claim wherein the drive circuitry is arranged:

to switch off the first insulated gate transistor (6) and after a second delay E to switch on the second insulated gate transistor (8);

to compare the time that the voltage on the first monitor point passes a third predetermined voltage and the time that the voltage on the second monitor point passes a fourth predetermined voltage; and

to decrease the second delay E if the fourth time is after the third time and to increase the second delay E if the fourth time is before the third time, so that the drive circuitry can set the delay D to be different from the second delay E.

7. A switching circuit comprising:

a drive circuit (18) according to any preceding claim; and

first and second insulated gate transistors (6, 8) each having gate, source and drain, the gates (38) of the first and second insulated gate transistors (6, 8) being connected to corresponding gate control outputs (26, 28) of the drive circuit.

8. A switching circuit according to claim 7 wherein the predetermined voltages are within 1V of the threshold voltage of the insulated gate transistors (6, 8).

9. A switching converter circuit, comprising:

control and sync insulated gate transistors (6, 8) each having gate, source and drain, the control and sync insulated gate transistors (6, 8) being connected together in series at a switch node (10) for driving a load; and

a drive circuit (18) connected to the gates of the insulated gate transistors for switching the control and sync insulated gate transistors on and off alternately;

wherein the drive circuit (18) is arranged;

to switch off the sync insulated gate transistor (8) and switch on the control insulated gate transistor (6) after a delay D;

to monitor the voltages at first and second monitoring points, the first monitor point being the switch node or the gate voltage of the control transistor (6) and the second monitor point being the gate voltage of the sync transistor (8);

to compare the time that the voltage on the first monitoring point falls, below a first predetermined voltage and the time that the voltage on the second monitoring point rises above a second predetermined voltage; and

to decrease the delay D if the second time is after the first time and to increase the delay D if the second time is before the first time.

10. A method of driving a converter circuit having first and second insulated gate transistors (6, 8) each having gate, source and drain, the method including the steps of:

(a) switching off the first insulated gate transistor (6);

(b) switching on the second insulated gate transistor (8) after a delay D;

(c) monitoring the voltages at first and second monitor points, the first monitor points being one of the gate of the first transistor (6) and a switch node (10) between first and second transistors, and the second monitor point being the gate of the second transistor (8); and

(d) comparing the time that the voltage on the first monitor point passes a first predetermined voltage and the time that the voltage on the second monitor point passes above a second predetermined voltage;

(e) decreasing the delay D if the second time is after the first time and increasing the delay D if the second time is before the first time; and

(f) switching on the first and second transistors (6, 8) alternately, repeating steps (a) to (e) above when switching on the second transistor and switching off the first transistor.

11. A method according to claim 10 further comprising:

(g) switching off the second insulated gate transistor (8) and switching on the first insulated gate transistor (6) after a second delay E which may be different from the delay D;

(h) monitoring the voltages at the first and second monitor points;

(i) comparing the third time that the voltage on the second monitor point falls below a third predetermined voltage and the fourth time that the voltage on the first monitor point rises above a fourth predetermined voltage;

(j) decreasing the second delay E if the fourth time is after the third time and increasing the second delay E if the fourth time is before the third time; and

repeating steps (g) to (j) above when switching on the first transistor (6) and switching off the second transistor (8) as the transistors are switched on alternately.

12. A method according to claim 10 or 11 wherein the delay is increased or decreased by a predetermined amount in the range 1 ns to 5 ns on each cycle.

13. A method according to any of claims 10 to 12 wherein the first monitor point is the gate of the control transistor respectively.

14. A method according to any of claims 10 to 12 wherein the first and second insulated gate transistors (6, 8) are connected together in series and have a switch node (10) therebetween for connection to a load, and in which the first monitor point is the switch node.