Electronic access control device

• US 20060038657A1
• Filed: 10/20/2005
• Published: 02/23/2006
• Est. Priority Date: 11/15/1994
• Status: Active Grant

• Current Assignee: O.S. Security LLC (Acacia Research Corporation)
• Original Assignee: Micro Enhanced Technology Incorporated
• Inventors: Denison, William D., Silvers, Bradley S., Brownfield, Lawrence C.
• Granted Patent: US 7,295,100 B2
• Time in Patent Office: Days
• US Class Current: 340/5.730
• CPC Class Codes: B60R 25/102 a signal being sent to a remote location, e.g. a radio signal being transmitted to a police station, a security company or the owner
• CPC Class Codes: B62H 5/20 indicating unauthorised use, e.g. acting on signalling devices alarm locks in general E05B45/00, e.g. alarm cable or chain lock E05B45/005
• CPC Class Codes: G07C 2009/00793 by Hertzian waves
• CPC Class Codes: G07C 9/00182 operated with unidirectional data transmission between data carrier and locks
• CPC Class Codes: G07C 9/00571 operated by interacting with a central unit
• CPC Class Codes: G07C 9/0069 actuated in a predetermined sequence
• CPC Class Codes: G07C 9/00896 specially adapted for particular uses
• CPC Class Codes: G07C 9/00912 for safes, strong-rooms, vaults or the like
• CPC Class Codes: G07C 9/33 by means of a password
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
• CPC Class Codes: G07F 7/1025 Identification of user by a PIN code
• CPC Class Codes: H04Q 1/00 Details of selecting apparatus or arrangements
• CPC Class Codes: Y10T 70/7006 Predetermined time interval controlled
• CPC Class Codes: Y10T 70/7113 Projected and retracted electrically

Abstract

An electronic lock utilizes two microprocessors remote from each other for enhanced security. The first microprocessor is disposed close to an input device such as a keypad, and the second microprocessor is disposed close to the lock mechanism and well protected from external access. The first microprocessor transmits a communication code to the second microprocessor when it receives via the input device an access code that matches a preset access code. The second microprocessor opens the lock if the transmitted communication code matches a preset communication code. The dual-microprocessor arrangement is advantageously used in a voice controlled access control system and in a motorcycle ignition control system. The present invention further provides an electronic access control system which has a master electronic key having a preset number of access, and an electronic alarm system for a bicycle that has a remote control mounted in the helmet of the rider.

Claims

1. An electronic control device comprising:

a circuit having a portion deactivated during a first time period;

the portion of the circuit enabled during a second time period, the portion of the circuit having an enable output signal generated in response to a sensed electromagnetic signal;

the portion of the circuit having an enable input code output generated in response the electromagnetic signal;

the portion of the circuit having an input code output generated in response to the electromagnetic signal;

a microprocessor having an output signal generated during an operation mode if the input code matches an authorization code and the microprocessor having a sleep mode to conserve power; and

,

a driver having an output generated in response to the output signal generated by the microprocessor.

2. The device of claim 1, wherein the first period of time is fixed.

3. The device of claim 1, wherein the second period of time is fixed.

4. The device of claim 1, the portion of the circuit comprising a receiver.

5. The device of claim 1, the portion of the circuit comprising an antenna.

6. The device of claim 1, further comprising at least one of the following responsive to the output of the driver:

a solenoid;

an electromechanical relay;

a DC motor;

a solid-state relay; and

, an alarm.

7. The device of claim 1, wherein an alarm is enabled in response to the output of the driver.

8. The device of claim 1, wherein an alarm is disabled in response to the output of the driver.

9. The device of claim 1, wherein the electromagnetic signal is infrared.

10. The device of claim 1, wherein the electromagnetic signal is within a radio frequency.

11. An apparatus comprising:

a first circuit comprising an oscillator and having a first circuit output signal;

a second circuit enabled and disabled in response to the first circuit output signal, the second circuit having a second circuit output signal generated in response to receipt of an electromagnetic signal;

a third circuit enabled during the receipt of the electromagnetic signal, the circuit having a third circuit output signal comprising an input code generated in response to receipt of an electromagnetic signal;

a fourth circuit enabled during an operation mode to compare the input code to an authorization code and having a sleep mode to conserve power; and

,

a driver having an output that is provided to a device if the input code matches the authorization code.

12. The apparatus of claim 11, the third circuit comprising a decode circuit.

13. The apparatus of claim 11, the device comprising at least one of the following:

a solenoid;

an electromechanical relay;

a DC motor;

a solid-state relay; and

, an alarm.

14. The apparatus of claim 11, wherein the device is an alarm that is enabled in response to the output of the driver.

15. The apparatus of claim 11, wherein the device is an alarm that is disabled in response to the output of the driver.

16. The apparatus of claim 11, wherein the electromagnetic signal is infrared.

17. The apparatus of claim 11, wherein the electromagnetic signal is within a radio frequency.

18. An apparatus comprising:

an oscillator having an output comprising a plurality of duty cycles;

a circuit that is periodically enabled for a time t₁ and disabled for a time t₂ during at least some of the duty cycles;

a portion of the circuit that generates an input code in response to an electromagnetic signal;

a microprocessor that compares the input code to an authorization code during an operation mode and having a sleep mode to conserve power;

a device responsive to a signal generated by the microprocessor, the device comprising at least one of the following;

a solenoid;

an electromechanical relay;

a DC motor;

a solid-state relay; and

, an alarm.

19. The apparatus of claim 18, wherein t₂ is fixed.

20. The apparatus of claim 18, wherein the portion of the circuit is a decoder.

21. The apparatus of claim 18 further comprising an electromechanical driver electrically connected to the microprocessor.

22. The apparatus of claim 18, wherein the electromagnetic signal is infrared.

23. The apparatus of claim 18, wherein the electromagnetic signal is within a radio frequency.

24. A method comprising the steps of:

deactivating a circuit during a first time period;

enabling a portion of the circuit for a second time period;

sensing an electromagnetic signal during the second time period;

processing the electromagnetic signal to obtain an input code;

comparing the input code to an authorization code during an operation mode and conserving power during a sleep mode; and

,

providing a signal to a device if the input code matches the authorization code.

25. The method of claim 24, wherein the first period of time is fixed.

26. The method of claim 24, wherein the second period of time is fixed.

27. The method of claim 24, further comprising the step of generating an oscillation signal and deactivating the circuit in response to the oscillation signal.

28. The method of claim 24, further comprising the step of operating at least one of the following in response to the signal to the device:

an electromechanical driver;

a solenoid;

a DC motor;

an electromechanical relay;

a solid-state relay; and

, an alarm.

29. The method of claim 24, wherein the device is an alarm and further comprises the step of deactivating the alarm.

30. The method of claim 24, wherein the device is an alarm and further comprising the step of activating the alarm.

31. The method of claim 24, wherein the electromagnetic signal is infrared.

32. The method of claim 24, wherein the electromagnetic signal is within a radio frequency.

33. The method of claim 24, further comprising the step of activating another portion of the circuit to compare the input code to the authorization code.

34. A method comprising the steps of:

periodically enabling and disabling a circuit during each of a plurality of duty cycles wherein the circuit is enabled for a time t₁ during each of the duty cycles;

receiving an input code transmitted via an electromagnetic signal;

comparing the input code to an authorization code during an operation mode and conserving power during a sleep mode;

enabling the circuit as the input code is being received for a time t₂; and

,

providing a signal to a device if the input code matches the authorization code.

35. The method of claim 34, wherein t₂ is fixed.

36. The method of claim 34, further comprising the step of sensing receipt of the electromagnetic signal.

37. The method of claim 34, wherein the electromagnetic signal is infrared.

38. The method of claim 34, wherein the electromagnetic signal is within a radio frequency.

39. The method of claim 34, further comprising the step of operating at least one of the following in response to the signal to the deice:

an electromechanical driver;

a solenoid;

a DC motor;

an electromechanical relay;

a solid-state relay; and

, an alarm.

40. The method of claim 34, wherein the device is an alarm and further comprising the step of deactivating the alarm.

41. The method of claim 34, wherein the device is an alarm and further comprising the step of activating the alarm.

42. A method comprising the steps of:

permanently storing a non-reprogrammable and permanent access code within a non-volatile memory;

providing a wake-up signal in response to pressing a key on a keypad;

waking-up at least one microprocessor for a period of time in response to the wake-up signal;

transmitting an input code to a microprocessor;

comparing the input code with a stored access code during the period of time;

activating a lock actuator if the input code matches the stored access code;

entering a sleep mode after the period of time, wherein during the sleep mode the microprocessor operates at a lower power consumption rate than when the microprocessor is awake.

43. An apparatus comprising:

a non-volatile memory containing a non-reprogrammable and substantially permanently stored access code;

a circuit generating a wake-up signal in response to pressing a key on a keypad;

at least one processor that is woke-up for a period of time in response to the wake-up signal, compares an input code with a stored access code, and generates a signal to activate a lock actuator if the input code matches a stored access code;

wherein at least one processor enters a sleep mode after the period of time, the sleep mode causing the processor to operate at a lower power consumption rate than when the processor is awake.

44. The apparatus of claim 43, wherein the apparatus comprises at least two microprocessors.

45. The apparatus of claim 43, wherein the apparatus also includes a low battery detection circuit that is enabled by a microprocessor in the operation mode by measuring a voltage of the battery and disabled in the sleep mode.

46. The apparatus of claim 43, wherein the lock actuator includes a solenoid control circuit for energizing a solenoid, the solenoid control circuit being controlled by a microprocessor and being enabled when a microprocessor is in the operation mode, the solenoid control circuit having first and second energized states controlled by a timer to energize the solenoid in the first energized state for a pre-selected first time interval at a first power level to move a plunger of the solenoid into a retracted position, and subsequently to energize the solenoid in the second energized state at a second power level to maintain the plunger in the retracted position for a second pre-selected time interval, the second power level being non-zero and lower than the first power level.

47. The apparatus of claim 43, further including a communication port connected to a microprocessor-based control circuit for sending an access code to a microprocessor-based control circuit for writing into the non-volatile memory to form the stored access code.

48. The apparatus of claim 43, further including a communication port connected to a microprocessor-based control circuit, and wherein a microprocessor is programmed to receive a read signal through the communication port and in response to the read signal to transmit the stored access code through the communication port.

49. The apparatus of claim 43, wherein the keypad includes a program key, and wherein a microprocessor is programmed to enter a code programming sequence in response to pressing the program key, receive a first input code from the keypad, compare the first input code with the stored access code in the memory, receive an additional access code from the keypad if the first input code matches the stored access code, and store the additional access code in the memory.

50. An apparatus comprising:

a non-volatile memory containing a non-reprogrammable and substantially permanently stored access code;

circuitry comprising two processors wherein at least one of the processors is shielded from external access;

a portion of the circuitry generating a wake-up signal in response to pressing a key on a keypad;

at least one of the processors being woke-up in response to the wake-up signal and receiving an input code;

at least one of the processors being woke-up and comparing the input code with the stored access code;

at least one of the processors generating a signal to activate a lock actuator if the input code matches the stored access code;

wherein at least one of the processors enters a sleep mode wherein the processor operates at a lower power consumption rate than when the processor is awake.

51. The apparatus of claim 50 further comprising a communication port operatively connected to the circuitry for sending the access code to the circuitry for writing into the non-volatile memory.

52. The apparatus of claim 50 further comprising a communication port operatively connected to the circuitry, and wherein one of the processors is programmed to receive a read signal through the communication port and in response to the read signal to transmit the stored access code through the communication port.

53. The apparatus of claim 50 wherein the keypad includes a program key, and wherein one of the processors is programmed to enter a code programming sequence in response to pressing the program key, receive a first input code from the keypad, compare the first input code with a stored access code in the memory, receive an additional access code from the keypad if the first input code matches the stored access code, and store the additional access code in the memory.

54. An apparatus comprising:

a non-volatile memory containing a stored access code;

a circuit comprising two processors wherein at least one of the processors is shielded from external access;

a portion of the circuitry generating a wake-up signal in response to pressing a key on a keypad;

at least one of the processors being woke-up in response to the wake-up signal and receiving an input code;

at least one of the processors being woke-up and comparing the input code with the stored access code;

at least one of the processor generating a signal to activate a lock actuator if the input code matches the stored access code;

at least a portion of the circuitry comprising a low battery detection circuit that is enabled by one of the processors in an operation mode and disabled in a sleep mode, the low battery detection circuit measuring a voltage of a battery in the operation mode; and

,

wherein at least one of the processors enters a sleep mode wherein the processor operates at a lower power consumption rate than when the processor is awake.

55. An apparatus comprising:

a non-volatile memory containing a stored access code;

a circuit comprising two processors wherein at least one of the processors is shielded from external access;

at least a portion of the circuit generating a wake-up signal in response to pressing a key on a keypad;

at least one of the processors being woke-up in response to the wake-up signal and receiving an input code;

at least one of the processors being woke-up and comparing the input code with the stored access code;

at least one of the processors generating a signal to activate a solenoid if the input code matches the stored access code;

at least a portion of the comprising a solenoid control circuit for energizing a solenoid, the solenoid control circuit being controlled by at least one of the processors and being enabled when the processor is in an operation mode, the solenoid control circuit having first and second energized states controlled by a timer to energize the solenoid in the first energized state for a pre-selected first time interval at a first power level to move a plunger of the solenoid into a retracted position, and subsequently to energize the solenoid in the second energized state at a second power level to maintain the plunger in the retracted position for a second pre-selected time interval, the second power level being non-zero and lower than the first power level; and

,

wherein at least one of the processors enters a sleep mode wherein processor operates at a lower power consumption rate than when the processor is awake.

56. A battery-powered electronic access control device for accessing a safe comprising:

a keypad having a plurality of keys and a program key mounted thereon;

at least one microprocessor-based control circuit comprising a microprocessor comprising a memory storing a code, the microprocessor being programmed to enter a sleep-mode to conserve battery power between operations and to awaken from a sleep mode upon pressing a key on the keypad used exclusively to enter a code programming operation;

the microprocessor-based control circuit operatively connected to the keypad for receiving user inputs entered through pressing the keys of the keypad, the microprocessor being configured to enter a code programming operation in response to pressing of the program key, receive an input key code through the keypad in response to detecting the pressing of the program key, and store the input key code in the memory as the access code for the access control device.

57. The electronic access control device of claim 56, the microprocessor-based control circuit further comprising a low-battery detection circuit that is enabled by the microprocessor in the operation mode for measuring a voltage of the battery and disabled when the microprocessor is in the sleep mode.

58. The electronic access control device of claim 56 further comprising a lock actuator comprising a solenoid control circuit for energizing a solenoid, the solenoid control circuit being controlled by the microprocessor and being enabled when the microprocessor is in the operation mode, the solenoid control circuit having first and second energized states controlled by a timer to energize the solenoid in the first energized state for a pre-selected first time interval at a first power level to move a plunger of the solenoid into a retracted position, and subsequently to energize the solenoid in the second energized state at a second power level to maintain the plunger in the retracted position for a second pre-selected time interval, the second power level being non-zero and lower than the first power level.

59. The electronic access control device of claim 56, wherein the keypad includes a program key connected to one of the interrupt inputs of the microprocessor, and wherein the microprocessor is programmed to enter a code programming sequence in response to a pressing of the program key, receive a first input code from the keypad, compare the first input code with the stored code in the memory, receive an additional code from the keypad if the first input code matches the stored code, and store the additional code in the memory.

60. The electronic access control device of claim 56, further including a communication port connected to the microprocessor-based control circuit for sending code to the microprocessor-based control circuit for writing into the memory to form the stored code.

61. The electronic access control device of claim 56, further including a communication port connected to the microprocessor-based control circuit, and wherein the microprocessor is programmed to receive a read signal through the communication port and in response to the read signal to transmit the stored code through the communication port.

62. The electronic access control device of claim 56, wherein the microprocessor control circuit comprises a plurality of microprocessors.

63. An electronic access control device comprising:

a microprocessor-based control circuit comprising a microprocessor and a non-volatile memory; and

,

at least two communication ports operatively coupled to the control circuit, the first port receiving an input code to control a lock actuator, and the second port dedicated to reading an access code from the non-volatile memory upon receiving a communication signal, wherein if the input code received by the first port matches the access code, then the lock actuator unlocks a lock.