Hybrid polar/cartesian digital modulator

• US 20060038710A1
• Filed: 08/11/2005
• Published: 02/23/2006
• Est. Priority Date: 08/12/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Staszewski, Robert B., Eliezer, Oren E.
• Granted Patent: US 7,532,679 B2
• Time in Patent Office: Days
• US Class Current: 341/143
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03M 1/005 among different converters types
• CPC Class Codes: H03M 1/68 with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
• CPC Class Codes: H03M 1/747 with equal currents which are switched by unary decoded digital signals
• CPC Class Codes: H03M 3/50 Digital/analogue converters using delta-sigma modulation as an intermediate step digital delta-sigma modulators per se H03M7/3004
• CPC Class Codes: H03M 7/3022 having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
• CPC Class Codes: H04L 27/361 Modulation using a single or unspecified number of carriers, e.g. with separate stages of phase and amplitude modulation

Abstract

A novel apparatus and method for a hybrid Cartesian/polar digital QAM modulator. The hybrid technique of the present invention utilizes a combination of an all digital phase locked loop (ADPLL) that features a wideband frequency modulation capability and a digitally controlled power amplifier (DPA) that features interpolation between 90 degree spaced quadrature phases. This structure is capable of performing either a polar operation or a Cartesian operation and can dynamically switch between them depending on the instantaneous value of a metric measured by a thresholder/router. In this manner, the disadvantages of each modulation technique are avoided while the benefits of each are exploited.

Claims

1. A method of hybrid polar/Cartesian modulation, said method comprising the steps of:

receiving I and Q input signals representing data to be transmitted;

generating a frequency control word and amplitude control word from said I and Q input signals;

determining a metric and comparing said metric to a threshold; and

performing either polar modulation or Cartesian modulation on said input signal in accordance with said comparison.

2. The method according to claim 1, further comprising the step of performing a combination of polar modulation and Cartesian modulation depending on the value of said metric.

3. The method according to claim 1, further comprising the step of storing a previous state in polar and Cartesian domains so as to maintain continuity of signal trajectory.

4. The method according to claim 1, wherein said step of determining comprises determining said metric based on said frequency control word, said amplitude control word and said I and Q input signals.

5. The method according to claim 1, adapted to be implemented in an Application Specific Integrated Circuit (ASIC).

6. The method according to claim 1, adapted to be implemented in a Field Programmable Gate Array (FPGA).

7. An apparatus for hybrid polar/Cartesian modulation, comprising:

a converter adapted to generate first frequency control data and first amplitude control data word from I and Q input signals representing data to be transmitted;

a digitally controlled oscillator (DCO) operative to generate four quadrature phases in response to said first frequency command data;

a transistor array comprising a plurality of transistors adapted to generate an output signal whose amplitude is substantially proportional to the number of transistors active at any one time in said array;

a switch matrix adapted to couple said four quadrature phases output of said DCO to said transistor array;

a router adapted to receive said first frequency command data, said first amplitude command data and said I and Q input signals, said router operative to select either polar operation or Cartesian operation and to generate second frequency command data and second amplitude command vector data in response thereto; and

control means coupled to said cordic and said switch array, said control means operative to control said switch matrix to dynamically switch between polar and Cartesian modulation in accordance with said second amplitude command vector data.

8. The apparatus according to claim 7, wherein said router is operative to determine whether to perform polar or Cartesian modulation based on said first frequency command data only.

9. The apparatus according to claim 7, wherein said router is operative to determine whether to perform polar or Cartesian modulation based on both said first frequency command data and said first amplitude command data.

10. The apparatus according to claim 7, wherein said router is operative to determine a metric based on said first frequency command data, to select polar modulation if said metric is less than or equal to a threshold and to select Cartesian modulation if said metric is greater than said threshold.

11. The apparatus according to claim 7, wherein said router is operative to determine a metric based on both said first frequency command data and said first amplitude command data, to select polar modulation if said metric is less than or equal to a threshold and to select Cartesian modulation if said metric is greater than said threshold.

12. The apparatus according to claim 7, wherein said transistor array comprises a first transistor array and a second transistor array wherein positive phases are coupled to said first transistor array and negative phases are coupled to said second transistor array resulting in a differential output signal.

13. The apparatus according to claim 7, wherein said switch matrix further comprises a plurality of attenuators, each attenuator adapted to be actively coupled to a transistor in said transistor array when none of the corresponding phases are selected to be coupled thereto.

14. The apparatus according to claim 7, wherein said switch matrix and said transistor array are divided into a plurality of parallel banks.

15. The apparatus according to claim 7, wherein said switch matrix and said transistor array are divided into three parallel banks, a first bank adapted to have a large range for slowly varying signal components, a second bank adapted to have a small range for fast varying signal components and a third bank adapted for fast sigma-delta dithering.

16. The apparatus according to claim 7, wherein said router comprises means for selecting a combination of polar operation and Cartesian operation depending on the value of said metric.

17. The apparatus according to claim 7, wherein said control means is adapted to store a previous state in polar and Cartesian domains so as to maintain continuity of signal trajectory.

18. The apparatus according to claim 7, wherein said switch matrix is adapted to perform Cartesian modulation when coupled to all four quadrature phases and the contributions from each can change dynamically.

19. The apparatus according to claim 7, wherein said switch matrix comprises dynamic element matching means for randomization of said plurality of transistors over time such that transistor mismatch error is spread out as background noise.

20. The apparatus according to claim 7, adapted to be implemented in an Application Specific Integrated Circuit (ASIC).

21. The apparatus according to claim 7, adapted to be implemented in a Field Programmable Gate Array (FPGA).

22. A modulator for hybrid polar/Cartesian modulation, comprising:

phase locked loop (PLL) means for generating quadrature phase signals in response to a frequency command; and

digital power amplifier (DPA) means for generating a radio frequency (RF) output signal in accordance with said quadrature phase signals and for dynamically switching between polar modulation operation and Cartesian modulation operation in accordance with the value of a metric based on said frequency command.

23. The modulator according to claim 22, adapted to be implemented in an Application Specific Integrated Circuit (ASIC).

24. The modulator according to claim 22, adapted to be implemented in a Field Programmable Gate Array (FPGA).

25. A modulator for hybrid polar/Cartesian modulation, comprising:

a digital phase locked loop (DPLL) adapted to generate quadrature phase clock signals;

a router adapted to receive a first frequency command data, a first amplitude command data and I and Q input signals, said router operative to select either polar modulation operation or Cartesian modulation operation and to generate second frequency command data and second amplitude command vector data in response thereto; and

a digital power amplifier (DPA), comprising;

an array of switch elements operative to generate an RF output signal proportional to the number of switch elements at any point in time;

a switch matrix coupled to the output of said DPLL and to said array of switch elements, said switch matrix operative to couple each quadrature phase clock signal to said array of switch elements in accordance with a plurality of control signals; and

a control unit adapted to generate said plurality of control signals in accordance with second amplitude command vector data, wherein said control unit adapted to dynamically switch between polar modulation operation and Cartesian modulation operation in response to said second amplitude command vector data.

26. The modulator according to claim 25, wherein said router comprises means for selecting a combination of polar operation and Cartesian operation depending on the value of said metric derived from said first frequency command data, said first amplitude command data and said I and Q input signals.

27. The modulator according to claim 25, wherein said control unit is adapted to store a previous state in polar and Cartesian domains so as to maintain continuity of signal trajectory.

28. The modulator according to claim 25, wherein said switch matrix is adapted to perform Cartesian modulation when coupled to all four quadrature phases of said DPLL and the contributions from each can change dynamically.

29. The modulator according to claim 25, wherein said switch matrix comprises dynamic element matching means for randomization of said switch elements over time such that switch element mismatch error is spread out as background noise.

30. The modulator according to claim 25, wherein said router is operative to determine whether to perform polar or Cartesian modulation based on said first frequency command data only.

31. The modulator according to claim 25, wherein said router is operative to determine whether to perform polar or Cartesian modulation based on both said first frequency command data and said first amplitude command data.

32. The modulator according to claim 25, wherein said router is operative to determine a metric based on said first frequency command data, to select polar modulation if said metric is less than or equal to a threshold and to select Cartesian modulation if said metric is greater than said threshold.

33. The modulator according to claim 25, wherein said router is operative to determine a metric based on both said first frequency command data and said first amplitude command data, to select polar modulation if said metric is less than or equal to a threshold and to select Cartesian modulation if said metric is greater than said threshold.

34. The modulator according to claim 25, wherein said array of switch elements comprises a first switch array and a second switch array wherein positive phases are coupled to said first switch array and negative phases are coupled to said second switch array resulting in a differential output signal.

35. The modulator according to claim 25, wherein said switch matrix further comprises a plurality of attenuators, each attenuator adapted to be actively coupled to a switch in said array of switch elements when none of the corresponding phases are selected to be coupled thereto.

36. The modulator according to claim 25, wherein said switch matrix and said array of switch elements are divided into a plurality of parallel banks.

37. The modulator according to claim 25, wherein said switch matrix and said array of switch elements are divided into three parallel banks, a first bank adapted to have a large range for slowly varying signal components, a second bank adapted to have a small range for fast varying signal components and a third bank adapted for fast sigma-delta dithering.

38. The modulator according to claim 25, adapted to be implemented in an Application Specific Integrated Circuit (ASIC).

39. The modulator according to claim 25, adapted to be implemented in a Field Programmable Gate Array (FPGA).

40. A multi-mode radio for use with a plurality of modulation schemes, comprising:

means for realizing a polar modulation mode of operation;

means for realizing a Cartesian modulation mode of operation;

means for realizing a hybrid polar/Cartesian modulation mode of operation wherein polar or Cartesian modulation is dynamically selected based on the value of a metric compared to a threshold; and

control means for selecting one of said polar modulation, said Cartesian modulation or said hybrid polar/Cartesian modulation modes of operation in accordance with a selected modulation scheme.

41. The radio according to claim 40, wherein said means for realizing a hybrid polar/Cartesian modulation mode of operation comprises:

receiving I and Q input signals representing data to be transmitted;

generating a frequency control word and amplitude control word from said I and Q input signals;

determining a metric and comparing said metric to a threshold; and

performing either polar modulation or Cartesian modulation on said input signal in accordance with said comparison.

42. The radio according to claim 40, adapted to be implemented in an Application Specific Integrated Circuit (ASIC).

43. The radio according to claim 40, adapted to be implemented in a Field Programmable Gate Array (FPGA).