Driver circuit of display device

• US 20060038766A1
• Filed: 07/12/2005
• Published: 02/23/2006
• Est. Priority Date: 08/23/2004
• Status: Active Grant

• Current Assignee: Japan Display Central Incorporated (Japan Display Incorporated)
• Original Assignee: Toshiba Matsushita Display Technology (Japan Display Incorporated)
• Inventors: Morita, Tetsuo
• Granted Patent: US 7,221,197 B2
• Time in Patent Office: Days
• US Class Current: 345/100
• CPC Class Codes: G09G 2330/02 Details of power systems and of start or stop of display operation
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

In a driver circuit of a display device, an electric potential difference between high-level power supply voltage VDD and low-level power supply voltage VSS2 in shift resistors and buffers is set smaller than an electric potential difference between high-level voltage VDD and low-level voltage VSS of enable signals OE in order to prevent increase in voltage stress on each transistor and concurrently to make larger an electric potential difference between high-level voltage and low-level voltage of output signals.

Claims

1. A driver circuit in a display device, comprising:

shift resistors to shift phases of input signals to be inputted thereinto, and for thereafter outputting the phase-shifted signals; and

buffers to amplify amplitudes of output signals from the shift resistors by use of enable signals, and for thereafter outputting the amplified signals to scan lines or signals lines,

wherein an electric potential difference between high-level voltage and low-level voltage of the enable signals is used as an electric potential difference with which to drive the scan lines or the signal lines, and

an electric potential difference between high-level power supply voltage and low-level power supply voltage in the shift resistors and the buffers is set smaller than the electric potential difference between the high-level voltage and the low-level voltage of the enable signals.

2. The driver circuit in the display device according to claim 1, wherein each of the buffers comprises an output circuit, the output circuit including:

a transistor having a conductive path between an enable terminal into which to input the enable signals and an output terminal from which to output the amplified signals; and

a transistor having a conductive path between the output terminal and the power supply voltage.

3. The driver circuit in the display device according to claim 1,

wherein each of transistors constituting the shift resistors and the buffers is a pMOS transistor, and

the low-level power supply voltage in the shift resistors and the buffers is set higher than the low-level voltage of the enable signals.

4. The driver circuit in the display device according to claim 1,

wherein each of transistors constituting the shift resistors and the buffers is an NMOS transistor, and

the high-level power supply voltage in the shift resistors and the buffers is set lower than the high-level voltage of the enable signals.