Memory device having staggered memory operations

• US 20060039227A1
• Filed: 08/17/2004
• Published: 02/23/2006
• Est. Priority Date: 08/17/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Bellows, Chad A., Richardson, Wayne S., Lai, Lawrence
• Granted Patent: US 8,190,808 B2
• Time in Patent Office: Days
• US Class Current: 365/230.30
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory system includes logical banks divided into sub-banks or collections of sub-banks. The memory system responds to memory-access requests (e.g., read and write) directed to a given logical bank by sequentially accessing sub-banks or collections of sub-banks. Sequential access reduces the impact of power-supply spikes induced by memory operations, and thus facilitates improved system performance. Some embodiments of the memory system combine sequential sub-bank access with other performance-enhancing features, such as wider power buses or increased bypass capacitance, to further enhance performance.

Claims

1. An integrated circuit comprising:

a. a bank-access controller adapted to receive memory access requests, including a first memory access request, and adapted to provide first and second access-control signals sequentially in response to the first memory access request;

b. a first memory bank having;

i. a first plurality of memory cells;

ii. a first access-control port coupled to the bank-access controller and adapted to receive the first access-control signals from the bank-access controller; and

iii. a first plurality of parallel data lines adapted to convey first data read in parallel from the first plurality of memory cells;

c. a second memory bank having;

i. a second plurality of memory cells;

ii. a second access-control port coupled to the bank-access controller and adapted to receive the second access-control signals from the bank-access controller; and

iii. a second plurality of parallel data lines adapted to convey second data read in parallel from the second plurality of memory cells; and

d. a serializer coupled to the bank-access controller, the first plurality of data lines, and the second plurality of data lines, wherein the serializer is adapted to combine the first and second data into a series of data.

2. The integrated circuit of claim 1, further comprising a third plurality of parallel data lines adapted to convey first write data in parallel to the first memory bank and a fourth plurality of parallel data lines adapted to convey second write data in parallel to the second memory bank.

3. The integrated circuit of claim 2, further comprising a deserializer adapted to separate serial input data into the first and second write data.

4. The integrated circuit of claim 1, further comprising a memory-access request bus adapted to receive memory-access requests and a request interface coupled between the memory-access request bus and the bank-access controller.

5. The integrated circuit of claim 1, wherein the first and second memory banks are two of N memory banks, where N is at least two.

6. The integrated circuit of claim 1, wherein the bank-access controller is adapted to issue read and write control signals to the first and second memory banks.

7. The integrated circuit of claim 6, wherein the read and write control signals include column selection signals.

8. The integrated circuit of claim 1, further comprising a multiplexer having first multiplexer input terminals coupled to the first plurality of data lines, second multiplexer input terminals coupled to the second plurality of data lines, and multiplexer output terminals coupled to the serializer, wherein the serializer is coupled to the first and second pluralities of data lines via the multiplexer.

9. The integrated circuit of claim 8, further comprising a register disposed between the multiplexer output terminals and the serializer.

10. The integrated circuit of claim 1, wherein the first and second memory banks each include first and second sub-banks.

11. The integrated circuit of claim 1, wherein each of the first and second memory banks is a sub-bank of a logical bank.

12. A method of reading a set of data from an integrated-circuit memory, the method comprising:

a. receiving a read request for the set of data;

b. activating, in response to the read request, a first sub-bank containing a first subset of the data;

c. activating, in response to the read request, a second sub-bank containing a second subset of the data;

d. reading, after activating the second sub-bank, the first sub-bank to obtain the first subset of data;

e. reading the second sub-bank to obtain the second subset of data; and

f. combining the first and second subsets of data into a serial data word.

13. The method of claim 12, further comprising precharging the first sub-bank and the second sub-bank.

14. A method of writing a set of data to an integrated-circuit memory, the method comprising:

a. receiving a write request;

b. receiving the set of data;

c. dividing the set of data into first and second parallel data words;

d. activating, in response to the write request, a first sub-bank;

e. activating, after activating the first sub-bank and in response to the write request, a second sub-bank;

f. writing the first parallel data word to the first sub-bank; and

g. writing, after writing the first parallel data word to the first sub-bank, the second parallel data word to the second sub-bank.

15. The method of claim 14, further comprising precharging the first sub-bank and the second sub-bank.

16. The method of claim 14, wherein activating one of the first and second sub-banks includes activating a plurality of bit sense amplifiers and selecting a plurality of memory columns.

17. A memory system comprising:

a. a request interface adapted to receive memory requests;

b. bank-access control circuitry coupled to the request interface, the bank-access control circuitry including;

i. a decoder coupled to the request interface and adapted to decode the memory requests;

ii. activation logic coupled to the decoder and adapted to issue first and second activation commands via respective first and second activation ports;

c. a first sub-bank including;

i. a first plurality of memory cells;

ii. a first plurality of data lines coupled to the memory cells; and

iii. a first memory control port coupled to the first activation port;

iv. wherein the first sub-bank activates the first plurality of memory cells in response to the first activation command; and

d. a second sub-bank including;

i. a second plurality of memory cells;

ii. a second plurality of data lines coupled to the memory cells; and

iii. a second memory control port coupled to the second activation port;

iv. wherein the second sub-bank activates the second plurality of memory cells in response to the second activation command.

18. The memory system of claim 17, further comprising a serializer coupled to the first and second pluralities of data lines.

19. The memory system of claim 17, further comprising a deserializer coupled to the first and second pluralities of data lines.

20. A memory module comprising:

a. a plurality of logical memory banks, each logical memory bank divided into a corresponding plurality of sub-banks, including a first sub-bank having a first plurality of data lines and a second sub-bank having a second plurality of data lines;

b. a request interface adapted to receive operation requests directed to the logical memory banks; and

c. bank-access control logic coupled to the request interface and adapted to receive and decode the operation requests, the bank access control logic including a first control port coupled to a first sub-bank and a second control port coupled to the second sub-bank, the bank-access control logic issuing, in response to one of the operation requests, a first activate command to the first sub-bank on a first clock cycle and a second activate command to the second sub-bank on a second clock cycle.

21. The memory module of claim 20, wherein the activate command is part of a read transaction that sequentially produces first and second read data.

22. The memory module of claim 21, further comprising a serializer adapted to combine the first and second read data into a serial data stream.

23. A memory circuit comprising:

a. a plurality of logical memory banks, each logical memory bank divided into a corresponding plurality of sub-banks, including a first sub-bank and a second sub-bank;

b. means for sequentially activating, in response to a memory request directed to one of the logical memory banks, the first sub-bank and the second sub-bank; and

c. means for sequentially accessing, in response to the memory request, the first sub-bank and the second sub-bank.

24. The memory circuit of claim 23, wherein the memory request is a read request.

25. The memory circuit of claim 24, wherein the first sub-bank produces first data in response to the read request and the second sub-bank produces second data in response to the read request.

26. The memory circuit of claim 25, further comprising means for combining the first and second data into a serial data stream.

27. The memory circuit of claim 23, wherein the memory request is a write request.

28. The memory circuit of claim 27, wherein the first sub-bank receives first data in response to the write request and the second sub-bank receives second data in response to the write request.

29. The memory circuit of claim 28, further comprising means for receiving the first and second data as serial input data and separating the first and second data prior to receipt of the first and second data by the respective first and second sub-banks.