High speed downlink packet access co-processor for upgrading the capabilities of an existing modem host

• US 20060039330A1
• Filed: 07/19/2005
• Published: 02/23/2006
• Est. Priority Date: 07/26/2004
• Status: Abandoned Application

• Current Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Original Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Inventors: Reznik, Alexander, Zeira, Ariela, Gazda, Robert G., Castor, Douglas R., Hepler, Edward L., DiFazio, Robert A., Kaewell, John David Jr., Hackett, William C.
• Application Number:
  US11/184,331
• Publication Number:
  US 20060039330A1
• Time in Patent Office: Days
• US Class Current: 370/335
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 2201/70707 Efficiency-related aspects
• CPC Class Codes: H04B 2201/709727 GRAKE type RAKE receivers
• CPC Class Codes: H04L 2025/03509 fractionally spaced H04L2025/03515 takes precedence
• CPC Class Codes: H04W 88/02 Terminal devices

Abstract

A wireless transmit/receive unit (WTRU) for processing code division multiple access (CDMA) signals. The WTRU includes a modem host and a high speed downlink packet access (HSDPA) co-processor, which communicate over a plurality of customizable interfaces. The modem host operates in accordance with third generation partnership project (3GPP) Release 4 (R4) standards, and the HSDPA co-processor enhances the wireless communication capabilities of the WTRU as a whole such that the WTRU operates in accordance with 3GPP Release 5 (R5) standards.

Claims

1. A wireless transmit/receive unit (WTRU) for processing code division multiple access (CDMA) signals, the WTRU comprising:

(a) a modem host; and

(b) a high speed downlink packet access (HSDPA) co-processor in communication with the modem host over a plurality of customizable interfaces, wherein the HSDPA co-processor enhances the wireless communication capabilities of the WTRU beyond those capabilities provided by the modem host alone.

2. The WTRU of claim 1 wherein the modem host operates in accordance with third generation partnership project (3GPP) Release 4 (R4) standards, and the HSDPA co-processor enhances the wireless communication capabilities of the WTRU such that the WTRU operates in accordance with 3GPP Release 5 (R5) standards.

3. The WTRU of claim 1 wherein the modem host includes a receiver including a root-raised cosine (RRC) filter.

4. The WTRU of claim 3 wherein the HSDPA co-processor includes an in-phase (I)/quadrature (Q) samples interface for receiving I/Q samples from an output of the RRC filter in the modem host.

5. The WTRU of claim 4 wherein the I/Q samples are provided by the RRC filter in the modem host to the I/Q samples interface of the HSDPA co-processor at a rate that is substantially twice the chip rate of the CDMA signals.

6. The WTRU of claim 1 wherein the HSDPA co-processor includes a receiver including a root-raised cosine (RRC) filter.

7. The WTRU of claim 6 wherein the HSDPA co-processor includes an in-phase (I)/quadrature (Q) samples interface for receiving I/Q samples from the modem host and providing the I/Q samples to an input of the RRC filter in the receiver of the HSDPA co-processor.

8. The WTRU of claim 7 wherein the I/Q samples are provided to the I/Q samples interface of the HSDPA co-processor at a rate that is substantially twice the chip rate of the CDMA signals.

9. The WTRU of claim 1 wherein the modem host includes a host central processing unit (CPU), and the HSDPA co-processor includes a host CPU interface for establishing communications between the host CPU and the HSDPA co-processor.

10. The WTRU of claim 1 wherein the modem host includes a timing and sync unit, and the HSDPA co-processor includes a timing management unit for receiving a frame sync pulse from the timing and sync unit of the modem host.

11. The WTRU of claim 10 wherein the HSDPA co-processor includes a clock generation unit in communication with the timing management unit, the clock generation unit for receiving a clock/reset signal from the modem host and generating a signal based on the frame sync pulse and the clock/reset signal.

12. The WTRU of claim 1 wherein the modem host includes a transmitter, and the HSDPA co-processor provides channel quality indicators (CQIs) and acknowledge (ACK)/non-acknowledge (NACK) signals to the transmitter in the modem host.

13. The WTRU of claim 1 wherein the modem host includes a layer 2/3 central processing unit (CPU), and the HSDPA co-processor includes a layer 2/3 CPU interface for communicating with the layer 2/3 CPU in the modem host.

14. The WTRU of claim 1 wherein the modem host comprises a means for powering-down the HSDPA co-processor or placing the co-processor in a low-power standby mode when HSDPA processing is not required.

15. A high speed downlink packet access (HSDPA) co-processor for enhancing the capabilities of a modem host in a wireless transmit/receive unit (WTRU), the HSDPA co-processor comprising:

(a) a receiver subsystem;

(b) a shared memory arbiter (SMA) memory in communication with the receiver subsystem;

(c) at least one interface for communicating with the modem host; and

(d) a receiver subframer in communication with the SMA memory.

16. The HSDPA co-processor of claim 15 wherein the receiver subsystem includes:

(a1) a root-raised cosine (RRC) filter;

(a2) a normalized least mean square (NLMS) chip level equalizer (CLE) receiver for receiving in-phase (I)/quadrature (Q) samples from the RRC filter;

(a3) an HSDPA despreader in communication with an output of the NLMS CLE receiver;

(a4) a chip level equalizer post processor (CLEPP) in communication with the NLMS CLE receiver and the HSDPA despreader;

(a5) a high speed shared control channel (HS-SCCH) decoder in communication with the HSDPA despreader and the CLEPP; and

(a6) a channel quality indicator (CQI) estimator in communication with the HSDPA despreader for providing CQI information to the modem host.

17. The HSDPA co-processor of claim 16 further comprising:

(e) a data mover in communication with the SMA memory.

18. The HSDPA co-processor of claim 15 wherein the receiver subsystem includes:

(a1) a root-raised cosine (RRC) filter;

(a2) a Rake receiver for receiving in-phase (I)/quadrature (Q) samples from the RRC filter;

(a3) an HSDPA despreader in communication with an output of the Rake receiver;

(a4) a chip level equalizer post processor (CLEPP) in communication with the Rake receiver and the HSDPA despreader;

(a5) a high speed shared control channel (HS-SCCH) decoder in communication with the HSDPA despreader and the CLEPP; and

(a6) a channel quality indicator (CQI) estimator in communication with the HSDPA despreader for providing CQI information to the modem host.

19. The HSDPA co-processor of claim 18 further comprising:

(e) a data mover in communication with the SMA memory.

20. A wireless transmit/receive unit (WTRU) comprising:

(a) a modem host which operates in accordance with third generation partnership project (3GPP) Release 4 (R4) standards; and

(b) a high speed downlink packet access (HSDPA) co-processor for upgrading the wireless communication capabilities of the WTRU such that the WTRU operates in accordance with 3GPP Release 5 (R5) standards.

21. An integrated circuit (IC) for processing code division multiple access (CDMA) signals, the IC comprising:

(a) a modem host; and

(b) a high speed downlink packet access (HSDPA) co-processor in communication with the modem host over a plurality of customizable interfaces, wherein the HSDPA co-processor enhances the wireless communication capabilities of the IC beyond those capabilities provided by the modem host alone.

22. The IC of claim 21 wherein the modem host operates in accordance with third generation partnership project (3GPP) Release 4 (R4) standards, and the HSDPA co-processor enhances the wireless communication capabilities of the IC such that the IC operates in accordance with 3GPP Release 5 (R5) standards.

23. The IC of claim 21 wherein the modem host includes a receiver including a root-raised cosine (RRC) filter.

24. The IC of claim 23 wherein the HSDPA co-processor includes an in-phase (I)/quadrature (Q) samples interface for receiving I/Q samples from an output of the RRC filter in the modem host.

25. The IC of claim 24 wherein the I/Q samples are provided by the RRC filter in the modem host to the I/Q samples interface of the HSDPA co-processor at a rate that is substantially twice the chip rate of the CDMA signals.

26. The IC of claim 21 wherein the HSDPA co-processor includes a receiver including a root-raised cosine (RRC) filter.

27. The IC of claim 26 wherein the HSDPA co-processor includes an in-phase (I)/quadrature (Q) samples interface for receiving I/Q samples from the modem host and providing the I/Q samples to an input of the RRC filter in the receiver of the HSDPA co-processor.

28. The IC of claim 27 wherein the I/Q samples are provided to the I/Q samples interface of the HSDPA co-processor at a rate that is substantially twice the chip rate of the CDMA signals.

29. The IC of claim 21 wherein the modem host includes a host central processing unit (CPU), and the HSDPA co-processor includes a host CPU interface for establishing communications between the host CPU and the HSDPA co-processor.

30. The IC of claim 21 wherein the modem host includes a timing and sync unit, and the HSDPA co-processor includes a timing management unit for receiving a frame sync pulse from the timing and sync unit of the modem host.

31. The IC of claim 30 wherein the HSDPA co-processor includes a clock generation unit in communication with the timing management unit, the clock generation unit for receiving a clock/reset signal from the modem host and generating a signal based on the frame sync pulse and the clock/reset signal.

32. The IC of claim 21 wherein the modem host includes a transmitter, and the HSDPA co-processor provides channel quality indicators (CQIs) and acknowledge (ACK)/non-acknowledge (NACK) signals to the transmitter in the modem host.

33. The IC of claim 21 wherein the modem host includes a layer 2/3 central processing unit (CPU), and the HSDPA co-processor includes a layer 2/3 CPU interface for communicating with the layer 2/3 CPU in the modem host.

34. The IC of claim 21 wherein the modem host comprises a means for powering-down the HSDPA co-processor or placing the co-processor in a low-power standby mode when HSDPA processing is not required.

35. An integrated circuit (IC) for enhancing the capabilities of a modem host in a wireless transmit/receive unit (WTRU), the IC comprising:

(a) a receiver subsystem;

(b) a shared memory arbiter (SMA) memory in communication with the receiver subsystem;

(c) at least one interface for communicating with the modem host; and

(d) a receiver subframer in communication with the SMA memory.

36. The IC of claim 35 wherein the receiver subsystem includes:

(a1) a root-raised cosine (RRC) filter;

(a2) a normalized least mean square (NLMS) CLE receiver for receiving in-phase (I)/quadrature (Q) samples from the RRC filter;

(a3) an HSDPA despreader in communication with an output of the NLMS CLE receiver;

(a4) a chip level equalizer post processor (CLEPP) in communication with the NLMS CLE receiver and the HSDPA despreader;

(a5) a high speed shared control channel (HS-SCCH) decoder in communication with the HSDPA despreader and the CLEPP; and

(a6) a channel quality indicator (CQI) estimator in communication with the HSDPA despreader for providing CQI information to the modem host.

37. The IC of claim 36 further comprising:

(e) a data mover in communication with the SMA memory.

38. The IC of claim 35 wherein the receiver subsystem includes:

(a1) a root-raised cosine (RRC) filter;

(a2) a Rake receiver for receiving in-phase (I)/quadrature (Q) samples from the RRC filter;

(a3) an HSDPA despreader in communication with an output of the Rake receiver;

(a4) a chip level equalizer post processor (CLEPP) in communication with the Rake receiver and the HSDPA despreader;

(a5) a high speed shared control channel (HS-SCCH) decoder in communication with the HSDPA despreader and the CLEPP; and

(a6) a channel quality indicator (CQI) estimator in communication with the HSDPA despreader for providing CQI information to the modem host.

39. The IC of claim 38 further comprising:

(e) a data mover in communication with the SMA memory.

40. An integrated circuit (IC) comprising:

(a) a modem host which operates in accordance with third generation partnership project (3GPP) Release 4 (R4) standards; and

(b) a high speed downlink packet access (HSDPA) co-processor for upgrading the wireless communication capabilities of the IC such that the IC operates in accordance with 3PP Release 5 (R5) standards.

41. A high speed downlink packet access (HSDPA) co-processor for enhancing the capabilities of a modem host in a wireless transmit/receive unit (WTRU), the HSDPA co-processor comprising:

(a) a normalized least mean square (NLMS) chip level equalizer (CLE) receiver for receiving in-phase (I)/quadrature (Q) samples;

(b) an HSDPA despreader in communication with an output of the NLMS CLE receiver;

(c) a chip level equalizer post processor (CLEPP) in communication with the NLMS CLE receiver and the HSDPA despreader;

(d) a high speed shared control channel (HS-SCCH) decoder in communication with the HSDPA despreader and the CLEPP; and

(e) a channel quality indicator (CQI) estimator in communication with the HSDPA despreader for providing CQI information to the modem host.

42. A high speed downlink packet access (HSDPA) co-processor for enhancing the capabilities of a modem host in a wireless transmit/receive unit (WTRU), the HSDPA co-processor comprising:

(a) a Rake receiver for receiving in-phase (I)/quadrature (Q) samples;

(b) an HSDPA despreader in communication with an output of the Rake receiver;

(c) a chip level equalizer post processor (CLEPP) in communication with the Rake receiver and the HSDPA despreader;

(d) a high speed shared control channel (HS-SCCH) decoder in communication with the HSDPA despreader and the CLEPP; and

(e) a channel quality indicator (CQI) estimator in communication with the HSDPA despreader for providing CQI information to the modem host.

43. An integrated circuit (IC) for enhancing the capabilities of a modem host in a wireless transmit/receive unit (WTRU), the IC comprising:

(a) a normalized least mean square (NLMS) chip level equalizer (CLE) receiver for receiving in-phase (I)/quadrature (Q) samples;

(b) a high speed downlink packet access (HSDPA) despreader in communication with an output of the NLMS CLE receiver;

(c) a chip level equalizer post processor (CLEPP) in communication with the NLMS CLE receiver and the HSDPA despreader;

(d) a high speed shared control channel (HS-SCCH) decoder in communication with the HSDPA despreader and the CLEPP; and

(e) a channel quality indicator (CQI) estimator in communication with the HSDPA despreader for providing CQI information to the modem host.

44. An integrated circuit (IC) for enhancing the capabilities of a modem host in a wireless transmit/receive unit (WTRU), the IC comprising:

(a) a Rake receiver for receiving in-phase (I)/quadrature (Q) samples;

(b) a high speed downlink packet access (HSDPA) despreader in communication with an output of the Rake receiver;

(c) a chip level equalizer post processor (CLEPP) in communication with the Rake receiver and the HSDPA despreader;

(d) a high speed shared control channel (HS-SCCH) decoder in communication with the HSDPA despreader and the CLEPP; and

(e) a channel quality indicator (CQI) estimator in communication with the HSDPA despreader for providing CQI information to the modem host.