Pipelined packet switching and queuing architecture
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Abstract
A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in a multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet'"'"'s routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Using bandwidth management techniques, each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port. The destination linecard may be the same physical linecard as that receiving the inbound packet or a different physical linecard. The transmit path includes a buffer/queuing circuit similar to that used in the receive path and can include another pipelined switch. Both enqueuing and dequeuing of packets is accomplished using CoS-based decision making apparatus, congestion avoidance, and bandwidth management hardware.
222 Citations
71 Claims
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1-33. -33. (canceled)
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34. An apparatus for switching packets, each packet having a header portion and an optional corresponding tail portion, the apparatus comprising:
a pipelined switch including;
a plurality of packet header buffers (PHBs);
a plurality of PHB pointers, each of the plurality of PHB pointers pointing to a PHB; and
a plurality of pipeline stage circuits connected in a sequence and comprising at least a first stage circuit, a last stage circuit, and a recycle path coupled between the first stage circuit and the last stage circuit, the last stage circuit being operable to send a recycle packet header portion along the recycle path, wherein;
the first stage circuit reads the header portion and stores the header portion in at least one of the plurality of PHBs using at least one of the plurality of PHB pointers; and
said last stage circuit outputs a modified header portion. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56)
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57. A method comprising:
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receiving a packet having a header portion and an optional corresponding tail portion;
switching the packet through a pipelined switch having a plurality of packet header buffers (PHBs), a plurality of PHB pointers wherein each of the plurality of PHB pointer points to a corresponding one of the plurality of PHBs, and a plurality of pipeline stages connected in a sequence, the plurality of pipeline stages including at least a first stage and a last stage, said switching further comprising;
reading and storing the header portion in one of the plurality of PHBs using at least one of the plurality of PHB pointers; and
selectively transmitting the header portion from the last stage to the first stage; and
outputting a modified header portion based on the header portion;
- View Dependent Claims (58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70)
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71. An apparatus comprising:
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a plurality of means for buffering;
a plurality of means for referencing, each of the plurality of means for referencing referencing a means for buffering; and
a plurality of means for processing packets, the plurality of means for processing packets being connected in a sequence and wherein;
a first one of the plurality of means for processing packets further comprises a means for reading the header portion and storing the header portion in at least one of the plurality of buffers; and
a second one of the plurality of means for processing packets further comprises a means for outputting a modified header portion and a means for selectively transmitting the header portion to the first one of the plurality of means for processing packets.
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Specification