Circuitized substrate, method of making same and information handling system using same

• US 20060040426A1
• Filed: 10/26/2005
• Published: 02/23/2006
• Est. Priority Date: 10/07/2003
• Status: Active Grant

• Current Assignee: I3 ELECTRONICS, INC.
• Original Assignee: Endicott Interconnect Technologies Incorporated
• Inventors: Konrad, John J., Antesberger, Timothy, Krasniak, Stephen, Fuller, James W. Jr., Kresge, John, Wells, Timothy L.
• Granted Patent: US 7,163,847 B2
• Time in Patent Office: Days
• US Class Current: 438/108
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H05K 2203/107 Using laser light
• CPC Class Codes: H05K 2203/175 Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
• CPC Class Codes: H05K 3/0035 of blind holes, i.e. having a metal layer at the bottom
• CPC Class Codes: H05K 3/0038 combined with laser drilling through a metal layer
• CPC Class Codes: H05K 3/242 : characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
• CPC Class Codes: H05K 3/28 : Applying non-metallic protective coatings H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673

Abstract

A method of making a circuitized substrate in which the substrate'"'"'s commoning bar, used during the plating of the circuitry on the substrate, is terminated from the various conductors using a laser. In a preferred embodiment, the laser acts through a dielectric layer (soldermask) which is applied over the circuitry, including the commoning bar and connected parts. The laser may also be used to expose selected ones of the circuit'"'"'s other parts, including various pads used to accommodate a wirebond (from a chip) and also solder balls for eventual placement of the substrate on a larger circuit board.

Claims

1. A method of making a circuitized substrate, said method comprising:

providing a first dielectric layer having a first surface and a second opposing surface;

forming a first pattern of conductors and a second pattern of conductors spaced from said first pattern and electrically coupled thereto on said first surface of said first dielectric layer;

forming a common conductive line on said second opposing surface of said first dielectric layer and electrically connected to each of said conductors of said second pattern of conductors; and

thereafter terminating said electrical connections between each of said conductors of said second pattern of conductors and said common conductive line using a laser.

2. The method of claim 1 further including positioning a second dielectric layer substantially over said first and second patterns of conductors and a third dielectric layer over said common conductive line prior to said terminating of said electrical connections.

3. The method of claim 2 wherein said second and third dielectric layers are provided in substantially liquid form and flowed onto said first dielectric layer.

4. The method of claim 3 wherein said second and third dielectric layers each comprise a soldermask.

5. The method of claim 1 further including using said laser to simultaneously provide openings above respective ones of said electrical connections during said terminating of said connections.

6. The method of claim 5 wherein said laser also partially removes some of said first dielectric layer immediately below said electrical connections during said terminating of said connections.

7. The method of claim 1 wherein said first and second pattern of conductors and said common conductive line are formed using electrolytic plating.

8. The method of claim 1 further including positioning a semiconductor chip on said first dielectric layer and electrically coupling said semiconductor chip to said first pattern of conductors.

9. The method of claim 8 wherein said electrically coupling of said semiconductor chip to said first pattern of conductors is accomplished using a wirebonding operation.

10. The method of claim 8 wherein said semiconductor chip is electrically coupled to said first pattern of conductors using a plurality of solder balls.

11. A method of making a circuitized substrate, said method comprising:

providing a first dielectric layer having a first surface and a second opposing surface;

forming a first pattern of conductors on said first surface and a second pattern of conductors on said second surface and electrically coupled to said first pattern of conductors on said first dielectric layer;

forming a common conductive line on said second opposing surface of said first dielectric layer electrically connected to each of said conductors of said second pattern of conductors; and

thereafter terminating said electrical connections between each of said conductors of said second pattern of conductors and said common conductive line using a laser.

12. The method of claim 11 further including positioning a second dielectric layer substantially over said first pattern of conductors and a third dielectric layer over said second pattern of conductors and said common conductive line prior to said terminating of said electrical connections.

13. The method of claim 12 wherein said second and third dielectric layers are provided in substantially liquid form and flowed onto said first dielectric layer.

14. The method of claim 13 wherein said second and third dielectric layers each comprise a soldermask.

15. The method of claim 12 further including using said laser to simultaneously provide openings above respective ones of said electrical connections during said terminating of said connections.

16. The method of claim 15 wherein said laser also partially removes some of said first dielectric layer immediately below said electrical connections during said terminating of said connections.

17. The method of claim 11 wherein said first and second pattern of conductors and said common conductive line are formed using electrolytic plating.

18. The method of claim 11 further including positioning a semiconductor chip on said first dielectric layer and electrically coupling said semiconductor chip to said first pattern of conductors.

19. The method of claim 18 wherein said electrically coupling of said semiconductor chip to said first pattern of conductors is accomplished using a wirebonding operation.

20. The method of claim 18 wherein said semiconductor chip is electrically coupled to said first pattern of conductors using a plurality of solder balls.