Method for fault analysis using simulation

• US 20060041417A1
• Filed: 08/19/2004
• Published: 02/23/2006
• Est. Priority Date: 08/19/2004
• Status: Active Grant

• Current Assignee: International Truck Intellectual Property Co. LLC (Volkswagen AG)
• Original Assignee: International Truck Intellectual Property Co. LLC (Volkswagen AG)
• Inventors: Palladino, James
• Granted Patent: US 7,200,543 B2
• Time in Patent Office: Days
• US Class Current: 703/14
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A utility for enhancing the interface of a electronic circuit simulator provides for selecting signals for monitoring, selecting groups of components for variation of tolerances and inserting faults to an underlying model of the circuit.

Claims

1. A method of evaluating electrical systems through failure mode and effects analysis on a model of an electrical system executing as a simulation on a data processing system, the method comprising the steps executed on a data processing system of:

generating a list of possible electrical signals from the model;

prompting a user to select signals from the list of possible electrical signals;

characterizing at least some of the components in the model of the electrical circuit with a set of global variables used to specify component tolerances;

generating and displaying a list of the tolerance controlled components to the user and prompting selection of tolerances for each component;

generating values for the components based on the selected tolerances and running at least two iterations of the model to determine an operating range of the model; and

calculating first and second iterations exhibiting the greatest variation in outcomes.

2. The method of claim 1, comprising the further steps of:

for a given iteration of the simulation forcing otherwise undetermined electrical signals to assume a predetermined value.

3. The method of claim 1, comprising the further steps of:

inserting faults to the model;

executing further iterations of the simulation with the inserted faults, varying component tolerances with each iteration;

selecting iterations from the simulations with inserted faults exhibiting the greatest variation; and

determining from results of the iterations whether failures occurred.

4. The method of claim 3, comprising the further steps of:

assigning groups of components to like variations to tolerance limits.

5. The method of claim 4, comprising the further steps of:

separating faults into detectable and detrimental classes; and

building a results table including flagging failures if any for display to a user of the data processing system.

6. The method of claim 3, comprising the further steps of:

categorizing results of iterations as non detection of failure responsive the range of outcomes for a model with an inserted fault falling within the range of outcomes for the model without faults;

categorizing results of iterations as a possible detection of failure responsive the range of outcomes for the model with an inserted fault overlapping the range of outcomes for the model without faults;

categorizing results of iterations as detection of failure responsive the range of outcomes for the model with an inserted fault falling outside the range of outcomes for the model without faults;

categorizing results of iterations as non detection of failure responsive the range of outcomes for the model with an inserted fault and the range of outcomes for the model without faults being indeterminate;

categorizing results of iterations as non detection of failure responsive the range of outcomes for the model without faults being indeterminate; and

categorizing results of iterations as a possible detection of failure responsive the range of outcomes for the model with an inserted fault being indeterminate and the range of outcomes for the model without faults being determinate.

7. The method of claim 1, wherein the step of prompting selection of tolerances provides a selected one of at least two tolerance adjustments including:

adding tolerance and assuming minimum tolerance.

8. The method of claim 1, further comprising the step of:

prompting selection of time slots for determining signal values.

9. A utility program for enhancing a user interface of an electrical circuit simulation program, comprising:

a plurality of views for display on a computer display including,

a signals list including a signals available sublist and a signals selected sublist,

a device parameter view in which every component of the electrical circuit may be viewed and its tolerances selected, and

a time slots view from which instances during a simulation may be selected for capturing values of the signals in the selected signals list are captured.

10. The utility program of claim 9, the plurality of views further comprising:

a test setup view allowing the number of iterations of the simulation to be selected.

11. The utility program of claim 10, the plurality of views further comprising:

a no fault view in which the results of the no fault simulations are displayed arrayed by the selected signals.

12. The utility program of claim 11, the plurality of views further comprising:

a fault select view for displaying possible points for the insertion of faults to the electrical circuit undergoing testing, and places for selection of the point for insertion and tagging of a fault.

13. The utility program of claim 12, the plurality of views further comprising:

a run faults tab for displaying results by node of faulted runs of the electrical circuit undergoing testing.

14. A method of implementing fault mode and effects analysis using an electronic circuit simulation program comprising the steps of:

generating a list of circuit signals for monitoring;

selecting component tolerances;

running the simulation program for the electronic circuit iteratively while varying component tolerances to develop operating ranges for the list of circuit signals;

inserting faults to the electronic circuit; and

running the simulation program for the fault modified electronic circuit while varying the component tolerances to determine out of range operation.