Multiprocessor chip having bidirectional ring interconnect

• US 20060041715A1
• Filed: 05/28/2004
• Published: 02/23/2006
• Est. Priority Date: 05/28/2004
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mattina, Matthew, Chrysos, George Z., Felix, Stephen
• Application Number:
  US10/855,509
• Publication Number:
  US 20060041715A1
• Time in Patent Office: Days
• US Class Current: 711/110
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses

Abstract

Embodiments of the present invention are related in general to on-chip integration of multiple components on a single die and in particular to on-chip integration of multiple processors via a bidirectional ring interconnect. An embodiment of a semiconductor chip includes a plurality of processors, an address space shared between the processors, and a bidirectional ring interconnect to couple the processors and the address space. An embodiment of a method includes calculating distances between a packet source and destination on multiple ring interconnects, determining on which interconnect to transport the packet, and then transporting the packet on the determined interconnect. Embodiments provide improved latency and bandwidth in a multiprocessor chip. Exemplary applications include chip multiprocessing.

Claims

1. An apparatus comprising at least one bidirectional ring structure on a semiconductor chip.

2. The apparatus of claim 1, further comprising a plurality of nodes coupled together by the at least one bidirectional ring structure.

3. The apparatus of claim 2, wherein each node comprises one of a processor, a cache bank, a shared memory interface, a shared global coherence engine interface, and a shared input/output interface.

4. The apparatus of claim 2, further comprising a subtractor to couple to at least one of the plurality of nodes and to compute a direction on the at least one bidirectional ring structure to transport packets between the at least one of the plurality of nodes and a destination node.

5. The apparatus of claim 2, further comprising a programmable finite state machine to couple to at least one of the plurality of nodes and to compute a direction on the at least one bidirectional ring structure to transport packets between the at least one of the plurality of nodes and a destination node.

6. The apparatus of claim 1, wherein the at least one bidirectional ring structure is to transport packets concurrently in a clockwise direction and in a counterclockwise direction.

7. The apparatus of claim 1, wherein the at least one bidirectional ring structure is to transport packets alternatively in a clockwise direction and in a counterclockwise direction.

8. A semiconductor chip comprising:

a plurality of processors;

an address space shared between the plurality of processors; and

a bidirectional ring structure to couple to the plurality of processors and the address space.

9. The semiconductor chip of claim 8, wherein each of the plurality of processors comprises a central processing unit.

10. The semiconductor chip of claim 8, wherein the address space comprises a plurality of cache banks.

11. The semiconductor chip of claim 10, wherein the plurality of cache banks is to form a distributed shared cache.

12. The semiconductor chip of claim 11, wherein each of the plurality of cache banks of the distributed shared cache is responsible for a subset of the address space.

13. The semiconductor chip of claim 8, wherein the bidirectional ring structure is to transport packets between the plurality of processors and the address space.

14. The semiconductor chip of claim 13, wherein a packet is to transport an address request.

15. The semiconductor chip of claim 13, wherein a packet is to transport data.

16. The semiconductor chip of claim 13, wherein a packet is to transport a cache coherence protocol message.

17. The semiconductor chip of claim 16, wherein the cache coherence protocol message is to convey an invalidation of a cached address in the address space.

18. The semiconductor chip of claim 16, wherein the cache coherence protocol message is to convey permission to modify an address line in the address space.

19. The semiconductor chip of claim 16, wherein the cache coherence protocol message is to convey a request to extract modified data of an address line in the address space.

20. The semiconductor chip of claim 8, wherein the bidirectional ring structure comprises at least a first wire to transmit packets in a clockwise direction and at least a second wire to transmit packets in a counterclockwise direction.

21. The semiconductor chip of claim 20, wherein the bidirectional ring structure comprises a plurality of first wires to transmit packets in the clockwise direction and a plurality of second wires to transmit packets in the counterclockwise direction.

22. The semiconductor chip of claim 8, further comprising a subtractor to couple to at least one of the plurality of processors and to compute a direction on the bidirectional ring structure to transport a packet between the at least one of the plurality of processors and the address space and between the at least one of the plurality of the processors and a second one of the plurality of processors.

23. The semiconductor chip of claim 8, further comprising a subtractor to couple to a first portion of the address space and to compute a direction on the bidirectional ring structure to transport a packet between the first portion of the address space and at least one of the plurality of processors and between the first portion of the address space and a second portion of the address space.

24. The semiconductor chip of claim 8, further comprising a programmable finite state machine to couple to at least one of the plurality of processors and to compute a direction on the bidirectional ring structure to transport a packet between the at least one of the plurality of processors and the address space and between the at least one of the plurality of the processors and a second one of the plurality of processors.

25. The semiconductor chip of claim 24, wherein the programmable finite state machine is to search a look-up table for the direction based on a distance between the at least one of the plurality of processors and the address space or between the at least one of the plurality of processors and the second one of the plurality of processors.

26. The semiconductor chip of claim 8, further comprising a programmable finite state machine to couple to a first portion of the address space and to compute a direction on the bidirectional ring structure to transport a packet between the first portion of the address space and at least one of the plurality of processors and between the first portion of the address space and a second portion of the address space.

27. The semiconductor chip of claim 26, wherein the programmable finite state machine is to search a look-up table for the direction based on a distance between the first portion of the address space and the at least one of the plurality of processors and between the first portion of the address space and the second portion of the address space.

28. The semiconductor chip of claim 8, wherein each of the plurality of processors is to compute a direction on the ring structure to transport a packet between the processor and another processor or between the processor and the address space.

29. A system comprising:

a multiprocessor chip comprising

at least one central processing unit,

a shared address space, and

at least one bidirectional ring structure to couple the at least one central processor unit and agents of the shared address space; and

a bus to transport packets from the multiprocessor chip.

30. The system of claim 29, further comprising a memory coupled to the bus.

31. The system of claim 30, wherein the multiprocessor chip further comprises a shared memory interface coupled to the at least one bidirectional ring structure, the shared memory interface to couple the multiprocessor chip to the memory.

32. The system of claim 29, wherein the multiprocessor chip further comprises a shared global coherence engine interface coupled to the at least one bidirectional ring structure, the shared global coherence engine interface to couple the multiprocessor chip to a plurality of other multiprocessor chips.

33. The system of claim 29, further comprising at least one input/output device coupled to the bus.

34. The system of claim 33, wherein the multiprocessor chip further comprises a shared input/output interface coupled to the at least one bidirectional ring structure, the shared input/output interface to couple the multiprocessor chip to the at least one input/output device.

35. A method comprising:

calculating distances on first and second ring structures on a chip between a source node and a destination node;

determining on which of the first and second ring structures to transport a packet between the source and destination nodes based on the calculated distances; and

transporting the packet from the source node to the destination node on the determined ring structure.

36. The method of claim 35, wherein the calculating comprises:

calculating a clockwise distance between the source and destination nodes on the first ring structure; and

calculating a counterclockwise distance between the source and destination nodes on the second ring structure.

37. The method of claim 35, wherein the determining comprises:

determining which of the first and second ring structures has a shortest distance between the source and destination nodes in separate directions on each of the first and second ring structures.

38. The method of claim 37, wherein the separate directions comprise a clockwise direction and a counterclockwise direction.

39. The method of claim 35, wherein the determining comprises:

determining which of the first and second ring structures has less traffic.

40. The method of claim 35, wherein the transporting comprises:

transporting the packet clockwise on the first ring structure or counterclockwise on the second ring structure.

41. The method of claim 35, wherein the transporting comprises:

waiting to transport the packet from the source node, if another packet on the determined ring structure arrives at the source node.

42. The method of claim 35, wherein the transporting comprises:

advancing the packet on the determined ring structure every clock cycle.

43. A machine readable medium having stored thereon a plurality of executable instructions to perform a method comprising:

calculating distances along a plurality of ring structures on a chip between a source node and a destination node;

identifying on which of the plurality of ring structures to transport a packet between the source and destination nodes according to the calculated distances; and

transporting the packet from the source node to the destination node on the identified ring structure.

44. The machine readable medium of claim 43, wherein the calculating comprises:

calculating a clockwise distance between the source and destination nodes on at least one of the ring structures; and

calculating a counterclockwise distance between the source and destination nodes on at least another of the ring structures.

45. The machine readable medium of claim 44, wherein the identifying comprises:

identifying which of the at least one and the at least another of the ring structures is to provide a shortest distance between the source and destination nodes.

46. The machine readable medium of claim 45, wherein the transporting comprises:

transporting the packet clockwise on the at least one of the ring structures or counterclockwise on the at least another of the ring structures based on the shortest distance.