Memory command delay balancing in a daisy-chained memory topology

• US 20060041730A1
• Filed: 08/19/2004
• Published: 02/23/2006
• Est. Priority Date: 08/19/2004
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Larson, Douglas Alan
• Granted Patent: US 7,669,027 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0671 In-line storage system
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM'"'"'s command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. With such ability to predict command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel. A separate DIMM-specific response delay unit in the DIMM may also be programmed to provide DIMM-specific delay compensation in the response path, further allowing the memory controller to accurately ascertain the timing of receipt of a response thereat, and, hence, to better manage further processing of the response.

Claims

1. A method, comprising:

linking a plurality of memory modules in a daisy-chained configuration, wherein each of said plurality of memory modules contains a corresponding plurality of memory elements;

receiving a command at one of said plurality of memory modules;

propagating said command to one or more memory modules in said daisy-chained configuration; and

configuring at least one of said plurality of memory modules to delay transmission of said command received thereat to one or more memory elements contained therein until a respective first predetermined delay has elapsed.

2. The method of claim 1, further comprising:

connecting a memory controller to only one of said plurality of memory modules.

3. The method of claim 2, wherein receiving said command includes:

configuring said memory controller to transmit said command to the memory module connected thereto; and

receiving said command at the memory module connected to said memory controller.

4. The method of claim 2, wherein said configuring includes:

determining physical proximity of said at least one of said plurality of memory modules to said memory controller;

determining a command delay time to propagate said command from said memory controller to one of said plurality of memory modules that last receives said command in said daisy-chained configuration;

determining said respective first predetermined delay based on said physical proximity, said command delay time, and the total number of memory modules in said plurality of memory modules; and

programming said at least one of said plurality of memory modules so as to impart said respective first predetermined delay to said command prior to transmitting said command to said one or more memory elements contained therein.

5. The method of claim 2, further comprising:

configuring said at least one of said plurality of memory modules to generate a response to said command received thereat; and

further configuring said at least one of said plurality of memory modules to delay transmission of said response to said memory controller until a respective second predetermined delay has elapsed.

6. The method of claim 5, wherein said further configuring includes:

determining physical proximity of said at least one of said plurality of memory modules to said memory controller;

determining a response delay time required to propagate a last response to said memory controller, wherein said last response is a response to said command generated by one of said plurality of memory modules that last receives said command in said daisy-chained configuration;

determining said respective second predetermined delay based on said physical proximity, said response delay time, and the total number of memory modules in said plurality of memory modules; and

programming said at least one of said plurality of memory modules so as to impart said respective second predetermined delay to said response prior to transmitting said response to said memory controller.

7. A method, comprising:

linking a plurality of electronic devices in a daisy-chained configuration;

receiving a command at a first electronic device in said plurality of electronic devices;

propagating said command to the remaining electronic devices in said daisy-chained configuration; and

configuring each electronic device in said plurality of electronic devices to delay executing said command to generate a corresponding response thereto until a respective first predetermined delay has elapsed.

8. The method of claim 7, wherein said respective first predetermined delay is zero for the electronic device that last receives said propagated command.

9. The method of claim 7, further comprising:

connecting a controller to said first electronic device; and

configuring said controller to transmit said command to said first electronic device,

wherein said receiving includes receiving said command transmitted by said controller at the first electronic device connected thereto.

10. The method of claim 9, wherein configuring each said electronic device includes:

determining physical proximity of each said electronic device to said controller;

determining a command delay time to propagate said command from said controller to the electronic device that last receives said command in said daisy-chained configuration;

determining said respective first predetermined delay for each said electronic device based on said physical proximity thereof, said command delay time, and the total number of electronic devices in said plurality of electronic devices; and

programming each said electronic device so as to delay processing said command until said respective first predetermined delay has elapsed.

11. The method of claim 9, further comprising:

further configuring each said electronic device to delay transmission of said corresponding response to said controller until a respective second predetermined delay has elapsed.

12. The method of claim 11, wherein further configuring each said electronic device includes:

determining physical proximity of each said electronic device to said controller;

determining a response delay time required to propagate said corresponding response to said controller from the electronic device that last receives said command in said daisy-chained configuration;

determining said respective second predetermined delay for each said electronic device based on said physical proximity thereof, said response delay time, and the total number of electronic devices in said plurality of electronic devices; and

programming each said electronic device so as to impart said respective second predetermined delay to said corresponding response prior to transmitting said corresponding response to said controller.

13. The method of claim 11, wherein said respective second predetermined delay is zero for the electronic device that last receives said propagated command.

14. A combination, comprising:

a memory controller configured to generate and transmit a command; and

a plurality of memory modules connected to one another in a serial configuration, wherein only one of said plurality of memory modules is connected to said memory controller and wherein each memory module contains a corresponding plurality of memory elements,

wherein the memory module connected to said memory controller is configured to receive said command from said memory controller and to propagate said command to other memory modules in said serial configuration, wherein at least one of said plurality of memory modules is configured to delay transmission of said command received thereat to one or more memory elements contained therein until a respective first predetermined delay has elapsed.

15. The combination of claim 14, wherein said respective first predetermined delay is determined based on the physical proximity of said at least one of said plurality of memory modules to said memory controller, a command delay time required to propagate said command from said memory controller to one of said plurality of memory modules that last receives said command in said serial configuration, and the total number of memory modules in said plurality of memory modules.

16. The combination of claim 14, wherein said respective first predetermined delay is stored in said at least one of said plurality of memory modules.

17. The combination of claim 14, wherein said respective first predetermined delay is zero for the memory module that last receives said propagated command in said serial configuration.

18. The combination of claim 14, wherein said at least one of said plurality of memory modules is configured to generate a response to said command received thereat and to delay transmission of said response to said memory controller until a respective second predetermined delay has elapsed.

19. The combination of claim 18, wherein said respective second predetermined delay is determined based on the physical proximity of said at least one of said plurality of memory modules to said memory controller, a response delay time required to propagate to said memory controller a corresponding response to said command from one of said plurality of memory modules that last receives said command in said serial configuration, and the total number of memory modules in said plurality of memory modules.

20. The combination of claim 18, wherein said respective second predetermined delay is stored in said at least one of said plurality of memory modules.

21. The combination of claim 18, wherein said respective second predetermined delay is zero for the memory module that last receives said propagated command in said serial configuration.

22. The combination of claim 14, wherein said serial configuration is a daisy-chained configuration.

23. A system, comprising:

a processor;

a bus;

a controller connected to said processor via said bus, wherein said controller is configured to generate and transmit a command; and

a plurality of electronic devices connected to one another in a daisy-chained configuration, wherein only one of said plurality of electronic devices is connected to said controller and wherein each of said plurality of electronic devices communicates to said controller using a signal transfer mechanism for said daisy-chained configuration,

wherein the electronic device connected to said controller is configured to receive said command from said controller and to propagate said command to other electronic devices in said daisy-chained configuration, wherein each electronic device in said plurality of electronic devices is configured to delay executing said command to generate a corresponding response thereto until a respective first predetermined delay has elapsed.

24. The system of claim 23, wherein said respective first predetermined delay for each electronic device is determined based on the physical proximity of each said electronic device to said controller, a command delay time required to propagate said command from said controller to the electronic device that last receives said command in said daisy-chained configuration, and the total number of electronic devices in said plurality of electronic devices.

25. The system of claim 23, wherein said respective first predetermined delay is stored in each said electronic device.

26. The system of claim 23, wherein said respective first predetermined delay is zero for the electronic device that last receives said propagated command.

27. The system of claim 23, wherein each said electronic device is configured to delay transmission of said corresponding response to said controller until a respective second predetermined delay has elapsed, wherein said respective second predetermined delay is determined based on the physical proximity of each said electronic device to said controller, a response delay time required to propagate said corresponding response to said controller from the electronic device that last receives said command in said daisy-chained configuration, and the total number of electronic devices in said plurality of electronic devices.

28. The system of claim 27, wherein said respective second predetermined delay is stored in each said electronic device.

29. The system of claim 27, wherein said respective second predetermined delay is zero for the electronic device that last receives said propagated command.