Fault diagnosis of compressed test responses

• US 20060041812A1
• Filed: 08/25/2005
• Published: 02/23/2006
• Est. Priority Date: 02/13/2003
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Wang, Chen, Mrugalski, Grzegorz, Tyszer, Jerzy, Pogiel, Artur, Rajski, Janusz
• Granted Patent: US 7,509,550 B2
• Time in Patent Office: Days
• US Class Current: 714/742
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test
• CPC Class Codes: G01R 31/318583 Design for test
• CPC Class Codes: G01R 31/31921 using compression techniques, e.g. patterns sequencer
• CPC Class Codes: G11C 2029/3202 Scan chain
• CPC Class Codes: G11C 29/40 using compression techniques
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error signature comprising multiple bits (including one or more error bits) is received. Plural potential-error-bit-explaining scan cell candidates are evaluated using a search tree. A determination is made as to whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells. An output is provided of any such one or more failing scan cells determined. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Tangible computer-readable media comprising lists of failing scan cells identified by any of the disclosed methods are also provided.

Claims

1. A computer-implemented method of diagnosing faults in a circuit-under-test comprising:

receiving at least one error signature comprising multiple bits, the bits of the error signature corresponding to bits of a compressed test response produced by a compactor in the circuit-under-test in response to at least one applied test pattern, the bits of the error signature further comprising one or more error bits that indicate errors at corresponding one or more bit locations of the compressed test response;

evaluating plural potential-error-bit-explaining scan cell candidates using a search tree;

determining whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells; and

providing an output of any such determined one or more failing scan cells.

2. The method of claim 1, further comprising selecting the error signature from a list of error signatures, the selection being based at least partially on the number of errors in the error signature.

3. The method of claim 1, wherein the act of receiving at least one error signature comprises receiving an error signature corresponding to a compressed test response for a single applied test pattern.

4. The method of claim 1, wherein the act of receiving at least one error signature comprises receiving an error signature corresponding to the initial compressed test response for one or more applied test patterns.

5. The method of claim 1, further comprising prioritizing the order in which the scan cell candidates are evaluated using the search tree, the order being at least partially dependent on whether the respective scan cell candidates were previously determined to be failing scan cells.

6. The method of claim 1, further comprising prioritizing the order in which the scan cell candidates are evaluated using the search tree, the order being at least partially dependent on whether the respective scan cell candidates are in a scan chain having one or more scan cells that were previously determined to be failing scan cells.

7. The method of claim 1, further comprising prioritizing the order in which the scan cell candidates are evaluated in the search tree, the order being at least partially dependent on the number of error bits in the error signature that are determined in part by scan cells output during the same time period as the respective scan cell candidates.

8. The method of claim 1, further comprising prioritizing the order in which the scan cell candidates are evaluated in the search tree, the order being at least partially dependent on whether the error signature received matches a generic error pattern indicative of two or more errors masking one another in the compactor.

9. The method of claim 1, further comprising prioritizing the order in which the scan cell candidates are evaluated in the search tree, the order being at least partially dependent on weights assigned to the scan cell candidates, the weights corresponding to a likelihood that a respective scan cell candidate is at least a part of a solution group of one or more failing scan cells that explains the error bits in the one or more error signature.

10. The method of claim 9, wherein the weights are updated prior to receiving a next error signature.

11. The method of claim 1, further comprising performing the acts of claim 1 during production testing of the circuit-under-test.

12. The method of claim 1, wherein the act of receiving at least one error signature comprises receiving at least first and second error signatures, and wherein the act of determining further comprises determining whether the one or more failing scan cells determined to explain the error bits in the first error signature also explain error bits of the second error signature, the second error signature being different from the first error signature.

13. The method of claim 1, wherein the act of receiving at least one error signature further comprises receiving at least one error signature with one or more unknown bits that indicate unknown values at corresponding bit locations of the compressed test response.

14. One or more tangible computer-readable media storing computer-executable instructions for causing a computer system to perform the method of claim 1.

15. The method of claim 1, further comprising storing a list of the one or more failing scan cells and using the list to locate a defect in the circuit-under-test.

16. A circuit containing a defect diagnosed at least in part by the method of claim 15.

17. A computer-implemented method of diagnosing faults in a circuit-under-test comprising:

receiving an error signature comprising multiple bits, the bits of the error signature corresponding to bits of a compressed test response produced by a compactor in the circuit-under-test, the bits of the error signature further comprising one or more error bits that indicate errors at corresponding bit locations of the compressed test response;

selecting at least one error bit of the error signature;

selecting at least one scan cell candidate from a set of scan cells known to contribute to the bit of the compressed test response corresponding to the selected at least one error bit; and

determining whether the selected at least one scan cell candidate explains the selected at least one error bit in the error signature by updating the error signature to include the contribution of the at least one selected error bit.

18. The method of claim 17, wherein the act of determining further comprises, if the selected at least one scan cell candidate does not explain the selected at least one error bit in the error signature, using the updated error signature as the error signature and iteratively repeating the method of claim 17 at least one time.

19. The method of claim 18, further comprising backtracking to an earlier iteration if no solution is found, the solution being one or more scan cells that explain the presence of the selected at least one error bit of one error signature.

20. The method of claim 18, further comprising backtracking to an earlier iteration if progress toward a solution does not meet a threshold after a predetermined number of scan cell candidates have been selected and determined not to explain the selected at least one error bit.

21. The method of claim 17, wherein the act of updating the error signature is performed by computing a bit-wise modulo-two sum of the error signature and an error print associated with the selected at least one scan cell candidate.

22. One or more tangible computer-readable media storing computer-executable instructions for causing a computer system to perform the method of claim 17.

23. The method of claim 17, further comprising the act of diagnosing a defect in the circuit-under-test using one or more scan cells determined to explain the presence of the selected at least one error bit of one error signature.

24. A computer-implemented method of diagnosing faults in a circuit-under-test, comprising:

receiving at least first and second error signatures, each error signature comprising error bits that indicate the presence of one or more errors in one or more corresponding compressed test responses produced by a compactor on the circuit-under-test in response to at least one applied test pattern, the first error signature further comprising one or more unknown bits;

generating a search tree that identifies one or more sets of scan cells that explain the error bits in the first error signature; and

determining whether any of the identified one or more sets of scan cells also explain the error bits of a second signature, the second signature being different from the first signature.

25. The method of claim 24, further comprising outputting a set of scan cells determined to explain the error bits of the first signature and the error bits of the second signature.

26. The method of claim 24, wherein the first signature and the second signature correspond to the response of the circuit-under-test to a single applied test pattern.

27. The method of claim 24, wherein the first signature and the second signature are respectively generated from consecutively applied test patterns.

28. The method of claim 24, wherein the compactor is a feedback-free compactor.

29. The method of claim 24, wherein the act of generating the search tree comprises:

selecting at least one of the error bits of the first error signature;

selecting a scan cell candidate from a set of scan cells known to contribute to at least one bit of the compressed test response corresponding to the selected at least one error bit; and

determining whether the scan cell candidate explains the at least one error bit in the error signature by updating the error signature to include the contribution of the selected error bit.

30. One or more tangible computer-readable media storing computer-executable instructions for causing a computer system to perform the method of claim 25.

31. The method of claim 24, further comprising the act of storing a list of identified scan cells that explain the error bits in the first and second error signatures.

32. A circuit containing a fault diagnosed at least in part by the method of claim 24.