Adaptive fault diagnosis of compressed test responses

• US 20060041813A1
• Filed: 08/25/2005
• Published: 02/23/2006
• Est. Priority Date: 02/13/2003
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Wang, Chen, Mrugalski, Grzegorz, Tyszer, Jerzy, Pogiel, Artur, Rajski, Janusz
• Granted Patent: US 7,302,624 B2
• Time in Patent Office: Days
• US Class Current: 714/742
• CPC Class Codes: G01R 31/28 Testing of electronic circuits, e.g. by signal tracer EMC, EMP or similar testing of electronic circuits G01R31/002; testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers or computer components G06F11/00; checking static stores for correct operation G11C29/00 ; testing receivers or transmitters of transmission systems H04B17/00
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test
• CPC Class Codes: G01R 31/318583 Design for test
• CPC Class Codes: G01R 31/31921 using compression techniques, e.g. patterns sequencer
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G11C 2029/3202 Scan chain
• CPC Class Codes: G11C 29/40 using compression techniques
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, one or more signatures are received that indicate the presence of one or more errors in one or more corresponding compressed test responses. Scan cells in the circuit-under-test that caused the errors are identified by analyzing the signatures. In this exemplary embodiment, the analysis includes selecting a scan cell candidate that potentially caused an error in a compressed test response based at least partially on a weight value associated with the scan cell candidate, the weight value being indicative of the likelihood that the scan cell candidate caused the error. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Tangible computer-readable media comprising lists of failing scan cells identified by any of the disclosed methods are also provided.

Claims

1. A computer-implemented method of diagnosing faults in a circuit-under-test, comprising:

receiving one or more signatures that indicate the presence of one or more errors in one or more corresponding compressed test responses resulting from the application of at least one test pattern applied to a circuit-under-test;

identifying scan cells in the circuit-under-test that caused the errors in the one or more compressed test responses by analyzing the one or more signatures, wherein the act of analyzing comprises selecting a scan cell candidate that potentially caused an error in a compressed test response based at least partially on a weight value associated with the scan cell candidate and indicative of the likelihood that the scan cell candidate caused the error in the compressed test response; and

storing a list of the scan cells in the circuit-under-test that caused the errors.

2. The method of claim 1, further comprising updating weight values associated with scan cell candidates based on results from one or more previously analyzed signatures.

3. The method of claim 1, wherein each respective signature is associated with a compressed test response output from a feedback-free compactor.

4. The method of claim 1, wherein each respective signature is associated with a compressed test response indicative of the response of the circuit-under-test to a single test pattern.

5. The method of claim 1, wherein the analyzing act comprises the act of selecting a branch of a search tree and performing a branch and bound search procedure along the selected branch.

6. The method of claim 5, wherein the act of analyzing further comprises the act of terminating the branch and bound search procedure along the selected branch after a predetermined number of scan cells have been considered along the selected branch.

7. The method of claim 1, wherein the analyzing act further comprises limiting the scan cells from which the scan cell candidate is selected to scan cells in one or more selected scan chains of the circuit-under-test, the one or more selected scan chains being fewer than all scan chains of the circuit-under-test.

8. The method of claim 1, wherein the analyzing act further comprises computing respective weight values for other possible scan cell candidates, and removing at least some of the other possible scan cell candidates from scan cell candidate consideration based at least in part on their respective weight values.

9. The method of claim 1, performed during production testing of the circuit-under-test.

10. One or more tangible computer-readable media storing computer-executable instructions for causing a computer system to perform the method of claim 1.

11. The method of claim 1, further comprising diagnosing a defect using the list of the scan cells in the circuit-under-test that caused the errors.

12. A circuit containing a fault diagnosed at least in part by the method of claim 1.

13. A computer-implemented method, comprising:

identifying one or more failing scan cells of a circuit-under-test from signatures indicative of one or more errors in corresponding compressed test responses received from a feedback-free compactor coupled to the circuit-under-test, the act of identifying comprising,

selecting one or more scan cell candidates from a set of scan cell candidates, wherein information about one or more previously identified failing scan cells at least partially determines which of the one or more scan cell candidates are selected,

determining whether the selected one or more scan cell candidates justify the one or more errors in a respective signature, and

storing scan cell candidates determined to justify the one or more errors in the respective signature in a solution set of one or more failing scan cells associated with the respective signature.

14. The method of claim 13, further comprising enlarging or reducing the set of scan cell candidates based at least partially on the information about previously identified failing scan cells.

15. The method of claim 13, wherein the information about previously identified failing scan cells comprises an identification of the failing scan cells, a scan chain location of the failing scan cells, or both.

16. The method of claim 13, wherein the act of identifying is performed using a branch and bound search procedure.

17. The method of claim 13, further comprising identifying a physical defect in the circuit-under-test that contributes to the one or more failing scan cells identified.

18. One or more tangible computer-readable media storing computer-executable instructions for causing a computer system to perform the method of claim 13.

19. A circuit containing a fault diagnosed at least in part by the method of claim 13.

20. A method, comprising:

as part of a fault diagnosis process,

identifying a value in a compressed test response that indicates that an error was captured in at least one scan cell of a circuit-under-test upon application of a test pattern;

selecting a scan cell candidate from a set of scan cells known to affect the value, the selection being based at least partially on at least one of the following criteria;

(a) whether the scan cell candidate is known to have captured errors upon application of other test patterns;

(b) whether the scan cell candidate is located in a scan chain known to have captured errors upon application of other test patterns;

or (c) the number of error bits in the error signature that are determined in part by scan cells output during the same time period as the scan cell candidate; and

determining whether the scan cell candidate at least partially explains the error in the compressed test response.

21. The method of claim 20, wherein the act of selecting is additionally based on whether an error signature corresponding to the compressed test response at least partially matches a generic error pattern indicative of two or more errors masking one another in a compactor.

22. The method of claim 20 performed during production testing of the circuit-under-test.

23. The method of claim 20, wherein the compressed test response is provided by a feedback-free compactor.

24. The method of claim 20, wherein the compressed test response is provided by a finite memory compactor.

25. One or more tangible computer-readable media storing computer-executable instructions for causing a computer system to perform the method of claim 20.

26. The method of claim 20, further comprising the act of storing a list of scan cells that explain errors in compressed test responses and diagnosing one or more defects in the circuit-under-test from the stored list of scan cells.

27. The method of claim 20, further comprising the act of diagnosing at least one defect in the circuit-under-test from scan cell candidates that at least partially explain the error in the compressed test response.

28. A circuit containing a fault diagnosed at least in part by the method of claim 27.