Fault diagnosis of compressed test responses having one or more unknown states
First Claim
1. A compactor for compacting test responses in a circuit-under-test, comprising:
- an injector network comprising combinational logic, the injector network further comprising injector-network outputs and injector-network inputs, at least some of the injector-network inputs being logically coupled to two or more injector-network outputs according to respective injector polynomials; and
a selection circuit comprising selection-circuit outputs coupled to the injector-network inputs and selection-circuit inputs coupled to scan-chain outputs of the circuit-under-test, the selection circuit being configured to selectively route signals from the scan-chain outputs to the injector-network inputs according to one of plural different input configurations.
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Accused Products
Abstract
Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, a compactor for compacting test responses in a circuit-under-test is disclosed. In this embodiment, the compactor includes an injector network comprising combinational logic and includes injector-network outputs and injector-network inputs. At least some of the injector-network inputs are logically coupled to two or more injector-network outputs according to respective injector polynomials. The exemplary compactor further comprises a selection circuit that includes selection-circuit outputs coupled to the injector-network inputs and selection-circuit inputs coupled to scan-chain outputs of the circuit-under-test. The selection circuit is configured to selectively route signals from the scan-chain outputs to the injector-network inputs according to one of plural different input configurations.
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Citations
24 Claims
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1. A compactor for compacting test responses in a circuit-under-test, comprising:
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an injector network comprising combinational logic, the injector network further comprising injector-network outputs and injector-network inputs, at least some of the injector-network inputs being logically coupled to two or more injector-network outputs according to respective injector polynomials; and
a selection circuit comprising selection-circuit outputs coupled to the injector-network inputs and selection-circuit inputs coupled to scan-chain outputs of the circuit-under-test, the selection circuit being configured to selectively route signals from the scan-chain outputs to the injector-network inputs according to one of plural different input configurations. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A circuit, comprising:
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a circuit-under-test that is part of the circuit, the circuit-under-test comprising scan chains; and
a compactor circuit coupled to the scan chains and configured to receive a test response output from the scan chains, the compactor circuit being operable to generate two or more compressed test responses from the test response, the two or more compressed test responses being generated according to different compaction functions, the compactor circuit also comprising at least one memory element. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A method of synthesizing a compactor, comprising:
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generating one or more polynomials representing possible injector networks for coupling a plurality of memory elements in the compactor to respective scan-chain outputs; and
the polynomials being generated so that the number of memory elements between connections to the respective scan-chain outputs in a register of the compactor is greater than a minimum value and less than a maximum value, the minimum value being greater than one and the maximum value being less than the total number of memory elements in the register. - View Dependent Claims (19, 20, 21, 22, 23, 24)
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Specification